Emerging real-time applications are increasingly moving to distributed heterogeneous platforms, under the promise of more powerful and flexible resource capabilities. This shift inevitably brings new challenges. The design space to deploy chains of threads is more complex, and sound estimates of worst-case execution times are harder to obtain. Additionally, the environment is more dynamic, requiring additional runtime flexibility on the part of the application itself. In this paper, we present an optimization-based approach to this problem. First, we present a model and real-time analysis for modern distributed edge applications. Second, we propose a design-time optimization problem to show how to set the main parameters characterizing such applications from a time-predictability perspective. Then, we present an orchestration and runtime decision-making mechanism that monitors execution times and allows for runtime reconfigurations, spanning from graceful degradation policies to re-distributions of workload. A prototypical implementation of the proposed approach based on the QNX RTOS and its evaluation on a realistic case study based on an edge-based valet parking application conclude the paper.

Phased execution models tame the increased complexity and unpredictability of commercial off-the-shelf (COTS) multi-core platforms by separating execution from access to shared resources, e.g., Acquisition-Execution-Restitution (AER) model, PRedictable Execution Model (PREM). Memory phases are used to preload all instructions and data into the local memory so that task computations can be performed only using the local memory without shared memory access. While preemption can improve the schedulability ratio, managing the local memory during preemption becomes nontrivial due to its limited size. In this work, we focus on the 3-phase model under partitioned fixed-priority scheduling. Existing works that allow preemption in this model make the conservative assumption that local memory is sufficiently large to hold the memory partitions for all tasks simultaneously. In contrast, we propose a novel preemption chain analysis that takes the characteristics of the phased execution model into account to compute tight bounds on the memory requirements of a task set under preemption. In addition, we propose a memory-aware mapping (MAM) algorithm that utilizes the preemption chain analysis to assign tasks to cores such that the resulting system meets both timing and memory constraints. Evaluations show that the preemption-chain analysis reduces the memory requirements by up to 50% compared to the state-of-the-art. We further show that the MAM algorithm provides 20% more task sets that satisfy both timing and memory constraints than mapping heuristics that don't take memory into account.

Design space exploration (DSE) is a key activity in embedded design processes, where a mapping between applications and platforms that meets the process design requirements must be found. Finding such mappings is very challenging due to the complexity of modern embedded platforms and applications. DSE tools aid in this challenge by potentially covering sections of the design space that could be unintuitive to designers, leading to more optimised designs. Despite this potential benefit, DSE tools remain relatively niche in the embedded industry. A significant obstacle hindering their wider adoption is integrating such tools into embedded design processes. We present two contributions that address this integration issue. First, we present the design space identification (DSI) approach for systematically constructing DSE solutions that are modular and tuneable. Modularity means that DSE solutions can be reused to construct other DSE solutions, while tuneability means that the most specific DSE solution is chosen for the target DSE problem. Moreover, DSI enables transparent cooperation between exploration algorithms. Second, we present IDeSyDe, an extensible DSE framework for DSE solutions based on DSI. IDeSyDe allows extensions to be developed in different programming languages in a manner compliant with the DSI approach. We showcase the relevance of these contributions through five different case studies. The case study evaluations showed that non-exploration DSI procedures create overheads, which are marginal compared to the exploration algorithms. Empirically, most evaluations average 2% of the total DSE request. More importantly, the case studies have shown that IDeSyDe indeed provides a modular and incremental framework for constructing DSE solutions. In particular, the last case study required minimal extensions over the previous case studies so that support for a new application type was added to IDeSyDe.

Industrial applications are often time critical and subject to end-to-end latency constraints. Job-level dependencies can be leveraged to specify a partial ordering on tasks' jobs already at early design phases, agnostic of the hardware platform or scheduling algorithm, and guarantee that end-to-end latency constraints of task chains are met as long as the job-level dependencies are respected. However, their realization at runtime can introduce overheads and complicates the scheduling and timing analysis. This work presents an approach that merges multi-periodic tasks that are connected by job-level dependencies to a single task. A Constraint Programming formulation is presented that optimally merges such task clusters while all job-level dependencies are respected. Such an approach removes the need to consider job-level dependencies at runtime without being bound to a specific scheduling algorithm. Evaluations highlight the applicability of the approach by systemlevel experiments and showcase the scalability of the approach using synthetic task clusters.

A challenge in designing resource-constrained embedded systems for digital signal processing (DSP) is their complexity due to their vast design spaces, where only a fraction of implementations are feasible or optimal. A crucial tool to aid in this challenge is automated design space exploration (DSE). However, no exact, multi-objective, and preference-free DSE approach exists for DSP applications on resource-constrained embedded platforms. We propose a novel DSE solution with these ideal characteristics to perform DSE of analyzable DSP applications for tile-based multiprocessing embedded platforms. Our proposal harmonizes the exactness of constraint programming (CP) and the exploration efficiency of genetic algorithms (GA). Through this synergy, no single-objective reduction strategy or a priori objective preferences is required. We evaluate the proposal through state-of-the-art single-objective case studies and multi-objective case studies inspired by these. The evaluations show that our proposal improves the single-objective state-of-the-art and finds high-quality approximate Pareto-frontiers for the multi-objective case study. Therefore, our proposal is a more performant single-objective DSE solution than the state-of-the-art, and it is the first exact, multi-objective, and preference-free DSE approach for the problem addressed.

Modern edge real-time automotive applications are becoming more complex, dynamic, and distributed, moving away from conventional static operating environments to support advanced driving assistance and autonomous driving functionalities. This shift necessitates formulating more complex task models to represent the evolving nature of these applications aptly. Modeling of real-time automotive systems is typically performed leveraging Architectural Languages (ALs) such as Amalthea, which are commonly used by the industry to describe the characteristics of processing platforms, operating systems, and tasks. However, these architectural languages are originally derived for classical automotive applications and need to evolve to meet the needs of next-generation applications. This paper proposes an automatic framework for the modeling and automatic code generation of dynamic automotive applications under the QNX RTOS. To this end, we extend Amalthea to describe chains of communicating tasks with multiple operating modes and to consider the QNX's reservation-based scheduler, called APS, which allows providing temporal isolation between applications co-located on the same hardware platform. Finally, an evaluation is presented to compare different implementation alternatives under QNX that are automatically generated by our code generation framework.

Phased execution models separate computation from access to shared resources to make task execution predictable. These task models minimize interference between tasks, making them suitable for modern complex multi-core platforms. In the phased execution model, tasks perform computations only using the local memory to avoid accessing the shared memory during task execution. All instructions and data, including the intermediate results, are stored in the local memory during execution. Thus, the local memory size becomes a crucial factor in contrast to conventional execution. In the literature, non-preemptive and fully preemptive execution of phased execution models are studied. While the non-preemptive approaches utilize the local memory well, schedulability is reduced due to blocking. On the other hand, fully preemptive execution phases allow for better schedulability but require significantly more local memory capacity to implement preemptions at runtime without violating the model's execution semantics. Thus, this work evaluates different approaches to limited preemptive scheduling of the phased execution model under partitioned fixed-priority scheduling. We demonstrate that preemption thresholds and non-preemptive regions can successfully be used to satisfy both timing and memory constraints of phased tasks.

Commercial off-the-shelf (COTS) multi-core platforms offer high performance and large availability of processing resources. Increased contention when accessing shared resources is a result of the high parallelism and one of the main challenges when realtime applications are deployed to these platforms. As a result, several execution models have been proposed to avoid contention by separating access to shared resources from execution. In this work, we consider the Acquisition-Execution-Restitution (AER) model where contention to shared resources is avoided by design. We propose an exact schedulability test for the AER model under global fixed-priority scheduling using timed automata where we describe the schedulability problem as a reachability problem. To the best of our knowledge, this is the first exact schedulability test for the AER model under global fixed-priority scheduling on multiprocessor platforms. The performance of the proposed approach is evaluated using synthetic experiments and provides up to 65% more schedulable task sets than the state-of-the-art.