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Publications (10 of 69) Show all publications
Rosvall, K., Mohammadat, T., Ungureanu, G., Öberg, J. & Sander, I. (2018). Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors. In: : . Paper presented at 2018 21st Euromicro Conference on Digital System Design (DSD).
Open this publication in new window or tab >>Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors
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2018 (English)Conference paper, Published paper (Refereed)
Abstract [en]

System level optimization for multiple mixed-criticality applications on shared networked multiprocessor platforms is extremely challenging. Substantial complexity arises from the interdependence between the multiple subproblems of mapping, scheduling and platform configuration under the consideration of several, potentially orthogonal, performance metrics and constraints. Instead of using heuristic algorithms and problem decomposition, novel unified design space exploration (DSE) approaches based on Constraint Programming (CP) have in the recent years shown promising results. The work in this paper takes advantage of the modularity of CP models, in order to support heterogeneous multiprocessor Network-on-Chip (NoC) with Temporally Disjoint Networks (TDNs) aware message injection. The DSE supports a range of design criteria, in particular the optimization and satisfaction of power and throughput. In addition, the DSE now provides a valid configuration for the TDNs that guarantees the performance required to fulfil the design goals. The experiments show the capability of the approach to find low-power and high-throughput designs, and validate a resulting design on a physical TDN-based NoC implementation.

National Category
Engineering and Technology Electrical Engineering, Electronic Engineering, Information Engineering Embedded Systems Computer Systems
Identifiers
urn:nbn:se:kth:diva-239007 (URN)10.1109/DSD.2018.00011 (DOI)2-s2.0-85056465815 (Scopus ID)978-1-5386-7377-5 (ISBN)
Conference
2018 21st Euromicro Conference on Digital System Design (DSD)
Note

QC 20181114

Available from: 2018-11-14 Created: 2018-11-14 Last updated: 2019-03-20Bibliographically approved
Kyriakakis, E., Ngo, K. & Öberg, J. (2017). Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller. In: Nurmi, J Vesterbacka, M Wikner, JJ Alvandpour, A NielsenLonn, M Nielsen, IR (Ed.), 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC). Paper presented at 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS). IEEE
Open this publication in new window or tab >>Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
2017 (English)In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC) / [ed] Nurmi, J Vesterbacka, M Wikner, JJ Alvandpour, A NielsenLonn, M Nielsen, IR, IEEE , 2017Conference paper, Published paper (Refereed)
Abstract [en]

From deep space missions to low-earth orbit satellites, the natural radiation of space proves to be a hostile environment for electronics. Memory elements in particular are highly susceptible to radiation charge that if latched can cause single-event upsets (SEU, bit-flips) which lead to data corruption and even mission critical failures. On Earth, SDRAM devices are widely used as a cost-effective, high performance storage elements in almost every computer system. However, their physical design makes them highly susceptible to SEUs. Thus, their usage in space application is limited and usually avoided, requiring the use of radiation hardened components which are generally a few generations older and often much more expensive than COTS. In this paper, an off-chip SEU/MBU mitigation mechanism is presented that aims to drastically reduce the probability of data corruption inside a commercial-off-the-shelf (COTS) synchronous dynamic random access memory (SDRAM) using a triple modular redundant (TMR) scheme for data and periodic scrubbing. The proposed mitigation technique is implemented in a novel controller that will be used by the single-event upset detector (SEUD) experiment aboard the KTH MInature STudent (MIST) satellite project.

Place, publisher, year, edition, pages
IEEE, 2017
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-223820 (URN)000425049100034 ()
Conference
2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS)
Note

QC 20180306

Available from: 2018-03-06 Created: 2018-03-06 Last updated: 2018-03-06Bibliographically approved
Öberg, J. (2017). Synthesis of VLIW accelerators from formal descriptions in a real-time multi-core environment. In: 14th FPGAworld Conference, FPGAworld 2017 - Academic Proceedings 2017: . Paper presented at 14th FPGAworld Conference, FPGAworld 2017, Stockholm, Sweden, 19 September 2017 (pp. 23-29). Association for Computing Machinery (ACM)
Open this publication in new window or tab >>Synthesis of VLIW accelerators from formal descriptions in a real-time multi-core environment
2017 (English)In: 14th FPGAworld Conference, FPGAworld 2017 - Academic Proceedings 2017, Association for Computing Machinery (ACM), 2017, p. 23-29Conference paper (Refereed)
Abstract [en]

Designing, programming and design space exploration of predictable Real-Time systems on Heterogeneous Multi-Core platforms is a very complex task. The increasing validation costs and time-to-market pressure creates a desire to build systems that are correct by construction. Formal description based on Model of Computations (MoCs) is a convenient way to create high-level models of such systems. The MoCs provide abstraction and high level modeling through a clear set of rules based on mathematics, which can be used as input for system synthesis. A formal synthesis flow would then ensure that the resulting real-time system is both predictable and correct by construction, provided that all transformations used in the flow can be verified/trusted. In this paper we show how a Real-Time computation node in an MPSoC system, described using the Synchronous MoC, can be transformed into a VLIW accelerator. The created accelerator is incorporated as a computation node in a heterogeneous multi-core system implemented on an FPGA.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2017
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-217844 (URN)10.1145/3135997.3135999 (DOI)2-s2.0-85033232596 (Scopus ID)9781450351546 (ISBN)
Conference
14th FPGAworld Conference, FPGAworld 2017, Stockholm, Sweden, 19 September 2017
Note

QC 20171127

Available from: 2017-11-27 Created: 2017-11-27 Last updated: 2017-11-27Bibliographically approved
Ngo, K., Mohammadat, T. & Öberg, J. (2017). Towards a Single Event Upset Detector Based on COTS FPGA. In: Nurmi, J Vesterbacka, M Wikner, JJ Alvandpour, A NielsenLonn, M Nielsen, IR (Ed.), 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC). Paper presented at 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS). IEEE
Open this publication in new window or tab >>Towards a Single Event Upset Detector Based on COTS FPGA
2017 (English)In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC) / [ed] Nurmi, J Vesterbacka, M Wikner, JJ Alvandpour, A NielsenLonn, M Nielsen, IR, IEEE , 2017Conference paper, Published paper (Refereed)
Abstract [en]

The Single Event Upset Detector (SEUD) is 3U CubeSat payload experiment that aims to achieve radiation tolerant computing through detection and correction of SEU bit flips on COTS SRAM FPGAs. Our proposed self-healing architecture applies selective TMR, internal configuration memory scrubbing, and partial reconfiguration and intends to demonstrate a cost-effective alternative to Space-grade radiation hardened SRAM FPGAs. This paper presents an overview of the ongoing development of the SEUD architecture and when complete, the SEUD will be tested on board the KTH MIST student CubeSat that is targeting to be launched in late 2020.

Place, publisher, year, edition, pages
IEEE, 2017
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-223821 (URN)000425049100019 ()
Conference
2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS)
Note

QC 20180306

Available from: 2018-03-06 Created: 2018-03-06 Last updated: 2018-03-06Bibliographically approved
Seyyedi, R., Mohammadat, M. T., Fakih, M., Gruettner, K., Öberg, J. & Graham, D. (2017). Towards Virtual Prototyping of Synchronous Real-time Systems on NoC-based MPSoCs. In: 2017 12TH IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS (SIES): . Paper presented at 12th IEEE International Symposium on Industrial Embedded Systems (SIES), JUN 14-16, 2017, INP Ecole Natl Superieure Electrotechnique Electronique Informatique Telec, Toulouse, FRANCE (pp. 99-102). IEEE
Open this publication in new window or tab >>Towards Virtual Prototyping of Synchronous Real-time Systems on NoC-based MPSoCs
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2017 (English)In: 2017 12TH IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS (SIES), IEEE , 2017, p. 99-102Conference paper, Published paper (Refereed)
Abstract [en]

NoC-based designs provide a scalable and flexible communication solution for the rising number of processing cores on a single chip. To master the complexity of the software design in such a NoC-based multi-core architecture, advanced incremental integration testing solutions are required. This work presents a virtual platform based software testing and debugging approach for a synchronous application model on a 2 x 2 NoC-based MPSoC. We propose a development approach and a test environment that exploits the time approximation within Imperas OVP instruction accurate simulator and a functional model of the Nostrum NoC, for both software instructions and hardware clock cycles at larger time stamps called Quantum that does not sacrifice functional correctness. The functional testing environment runs the target software without running it on the real hardware platform. With the help of Nostrum NoC we can support a synchronous system execution that is reasonably fast and precise with respect to a global synchronization signal, called HeartBeat. As work in progress, this work also discusses several possible timing refinement and their possible implication on the simulation semantics and performance and how it is tackled in the future work.

Place, publisher, year, edition, pages
IEEE, 2017
Series
International Symposium on Industrial Embedded Systems, ISSN 2150-3109
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-225781 (URN)000427108300015 ()978-1-5386-3166-9 (ISBN)
Conference
12th IEEE International Symposium on Industrial Embedded Systems (SIES), JUN 14-16, 2017, INP Ecole Natl Superieure Electrotechnique Electronique Informatique Telec, Toulouse, FRANCE
Note

QC 20180409

Available from: 2018-04-09 Created: 2018-04-09 Last updated: 2018-04-09Bibliographically approved
Diallo, P. I., Attarzadeh-Niaki, S. H., Robino, F., Sander, I., Champeau, J. & Öberg, J. (2015). A formal, model-driven design flow for system simulation and multi-core implementation. In: 2015 10th IEEE International Symposium on Industrial Embedded Systems: . Paper presented at 10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015; Siegen; Germany (pp. 254-263). IEEE
Open this publication in new window or tab >>A formal, model-driven design flow for system simulation and multi-core implementation
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2015 (English)In: 2015 10th IEEE International Symposium on Industrial Embedded Systems, IEEE , 2015, p. 254-263Conference paper, Published paper (Refereed)
Abstract [en]

With the growing complexity of Real-Time Embedded Systems (RTES), there is a huge interest in using modeling languages such as the Unified Modeling Language (UML), and other Model-Driven Engineering (MDE) techniques targeting RTES system design. These approaches provide language abstractions for system design, allowing to focus on their relevant properties. Unfortunately, such approaches still suffer from several shortcomings including the lack of well-defined semantics. Therefore, it remains difficult to connect the MDE specification tools and the design tools that are based on formal grounds and well-defined semantics to perform analysis, validation or system synthesis for RTES. This paper presents a top-down RTES design flow aiming to reduce the gap between MDE and formal design approaches. We present the connection between a framework dedicated to the enrichment of modeling languages such as UML with formal semantics, a framework based on formal models of computation supporting validation by simulation, and a system synthesis tool targeting a flexible platform with well-defined execution services. Our purpose is to cover several system design phases from specification, simulation down to implementation on a platform. As a case study, a JPEG Encoder application was realized following the different design steps of the tool-chain.

Place, publisher, year, edition, pages
IEEE, 2015
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-187135 (URN)10.1109/SIES.2015.7185067 (DOI)000380569800033 ()2-s2.0-84959543996 (Scopus ID)978-1-4673-7711-9 (ISBN)
External cooperation:
Conference
10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015; Siegen; Germany
Note

QC 20160518

Available from: 2016-05-18 Created: 2016-05-17 Last updated: 2016-09-06Bibliographically approved
Navas, B., Sander, I. & Öberg, J. (2015). Reinforcement Learning Based Self-Optimization of Dynamic Fault-Tolerant Schemes in Performance-Aware RecoBlock SoCs. Stockholm: KTH Royal Institute of Technology
Open this publication in new window or tab >>Reinforcement Learning Based Self-Optimization of Dynamic Fault-Tolerant Schemes in Performance-Aware RecoBlock SoCs
2015 (English)Report (Other academic)
Abstract [en]

Partial and run-time reconfiguration (RTR) technology has increased the range of opportunities and applications in the design of systems-on-chip (SoCs) based on Field-Programmable Gate Arrays (FPGAs). Nevertheless, RTR adds another complexity to the design process, particularly when embedded FPGAs have to deal with power and performance constraints uncertain environments. Embedded systems will need to make autonomous decisions, develop cognitive properties such as self-awareness and finally become self-adaptive to be deployed in the real world. Classico-line modeling and programming methods are inadequate to cope with unpredictable environments. Reinforcement learning (RL) methods have been successfully explored to solve these complex optimization problems mainly in workstation computers, yet they are rarely implemented in embedded systems. Disruptive integration technologies reaching atomic-scales will increase the probability of fabrication errors and the sensitivity to electromagnetic radiation that can generate single-event upsets (SEUs) in the configuration memory of FPGAs. Dynamic FT schemes are promising RTR hardware redundancy structures that improve dependability, but on the other hand, they increase memory system traffic. This article presents an FPGA-based SoC that is self-aware of its monitored hardware and utilizes an online RL method to self-optimize the decisions that maintain the desired system performance, particularly when triggering hardware acceleration and dynamic FT schemes on RTR IP-cores. Moreover, this article describes the main features of the RecoBlock SoC concept, overviews the RL theory, shows the Q-learning algorithm adapted for the dynamic fault-tolerance optimization problem, and presents its simulation in Matlab. Based on this investigation, the Q-learning algorithm will be implemented and verified in the RecoBlock SoC platform.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. p. 30
Series
TRITA-ICT/ECS ; 15:27
Keywords
cognitive hardware, partial and run-time reconfiguration, FPGA, autonomic computing, self-awareness, self-healing, machine learning, dynamic fault-tolerance, partial and run-time reconfiguration, complex adaptive systems, self-awareness, self-healing, machine learning, dynamic fault-tolerance, complex adaptive systems
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering Computer Systems Embedded Systems
Identifiers
urn:nbn:se:kth:diva-177999 (URN)KTH/ICT/ECS/R-15-27-SE (ISRN)
Note

QC 20151201

Available from: 2015-12-01 Created: 2015-12-01 Last updated: 2015-12-01Bibliographically approved
Navas, B., Sander, I. & Öberg, J. (2015). Towards cognitive reconfigurable hardware: Self-aware learning in RTR fault-tolerant SoCs. In: Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015: . Paper presented at Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Bremen, June 29 2015-July 1 2015. Institute of Electrical and Electronics Engineers (IEEE), Article ID 7238103.
Open this publication in new window or tab >>Towards cognitive reconfigurable hardware: Self-aware learning in RTR fault-tolerant SoCs
2015 (English)In: Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015, Institute of Electrical and Electronics Engineers (IEEE), 2015, article id 7238103Conference paper, Published paper (Refereed)
Abstract [en]

Traditional embedded systems are evolving into power-and-performance-domain self-aware intelligent systems in order to overcome complexity and uncertainty. Without human control, they need to keep operative states in applications such as drone-based delivery or robotic space landing. Nowadays, the partial and run-time reconfiguration (RTR) of FPGA-based Systems-on-chip (SoC) can enable dynamic hardware acceleration or self-healing structures, but this conversely increases system-memory traffic. This paper introduces the basis of cognitive reconfigurable hardware and presents the design of an FPGA-based RTR SoC that becomes conscious of its monitored hardware and learns to make decisions that maintain a desired system performance, particularly when triggering hardware acceleration and dynamic fault-tolerant (FT) schemes on RTR cores. Self-awareness is achieved by evaluating monitored metrics in critical AXI-cores, supported by hardware performance counters. We suggest a reinforcement-learning algorithm that helps the system to search out when and which reconfigurable FT-scheme can be triggered. Executing random sequences of an embedded benchmark suite simulates unpredictability and bus traffic. The evaluation shows the effectiveness and implications of our approach.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
Keywords
cognitive hardware, partial and run-time reconfiguration, FPGA, complex adaptive systems, self-awareness, self-healing, machine learning, dynamic fault-tolerance
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering Computer Systems Embedded Systems
Identifiers
urn:nbn:se:kth:diva-177998 (URN)10.1109/ReCoSoC.2015.7238103 (DOI)000380396200026 ()2-s2.0-84954191077 (Scopus ID)978-1-4673-7942-7 (ISBN)
External cooperation:
Conference
Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Bremen, June 29 2015-July 1 2015
Note

QC 20151201

Available from: 2015-12-01 Created: 2015-12-01 Last updated: 2016-09-07Bibliographically approved
Ezzeddine, H., Öberg, J. & Robino, F. (2015). Validation of Pipelined Double-precision Floating Point operations in a multi-core environment implemented on FPGA using the ForSyDe/NoC system generator tool suite. In: NORCHIP 2014 - 32nd NORCHIP Conference: The Nordic Microelectronics Event. Paper presented at 32nd NORCHIP Conference, NORCHIP 2014; Tampere; Finland; 27 October 2014 through 28 October 2014.
Open this publication in new window or tab >>Validation of Pipelined Double-precision Floating Point operations in a multi-core environment implemented on FPGA using the ForSyDe/NoC system generator tool suite
2015 (English)In: NORCHIP 2014 - 32nd NORCHIP Conference: The Nordic Microelectronics Event, 2015Conference paper, Published paper (Refereed)
Abstract [en]

Testing HW IP Blocks in multi-core environments is difficult. This paper presents a case study where a SINE/COSINE implementation using Pipelined Double-precision operations is implemented in one node, and results are sent through the NoC to a target node for inspection. The purpose of the experiments are two-fold, a) to study how debugging in a multi-core environment can be done and b) to examine why the original SINE/COSINE implementation is generating wrong results. During the experiments, several test-methods are applied to validate the implementations until the Floating Point implementation are generating correct values. After eliminating all faults in the operations, the SINE/COSINE function still generates some residual algorithmic errors, coming from the way the function was implemented. However, the experiments show that these errors can be eliminated with the help of some simple trigonometric rales.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-167373 (URN)10.1109/NORCHIP.2014.7004748 (DOI)2-s2.0-84921449379 (Scopus ID)9781479954421 (ISBN)
Conference
32nd NORCHIP Conference, NORCHIP 2014; Tampere; Finland; 27 October 2014 through 28 October 2014
Note

QC 20150601

Available from: 2015-06-01 Created: 2015-05-22 Last updated: 2015-06-01Bibliographically approved
Robino, F. & Öberg, J. (2014). From Simulink to NoC-based MPSoC on FPGA. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014: . Paper presented at Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. IEEE
Open this publication in new window or tab >>From Simulink to NoC-based MPSoC on FPGA
2014 (English)In: Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, IEEE , 2014Conference paper, Published paper (Refereed)
Abstract [en]

Network-on-chip (NoC) based multi-processor systems are promising candidates for future embedded system platforms. However, because of their complexity, new high level modeling techniques are needed to design, simulate and synthesize embedded systems targeting NoC-based MPSoC. Simulink is a popular modeling environment suitable to model at system level. However, there is no clear standard to synthesize Simulink models into SW and HW towards a NoC-based MPSoC implementation. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In this paper we present a novel design flow to synthesize Simulink models onto a NoC-based MPSoC running on low-cost FPGAs. Our design flow constrains the MPSoC and the Simulink model to share a common semantics domain. This permits to reduce the need of resource consuming SW components, reducing the memory requirements on the platform. At the same time, performances (throughput) of dataflow applications can increase when the number of processors of the target platform is increased. This is shown through a case study on FPGA.

Place, publisher, year, edition, pages
IEEE, 2014
Keywords
embedded systems;field programmable gate arrays;integrated circuit design;integrated circuit modelling;network-on-chip;FPGA;NoC-based MPSoC;SW components;Simulink;common semantics domain;dataflow applications;design flow;embedded system;memory requirements;multiprocessor systems;network-on-chip;Computational modeling;Field programmable gate arrays;Mathematical model;Program processors;Prototypes;Semantics;Software packages
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-145519 (URN)10.7873/DATE2014.341 (DOI)000354965500328 ()2-s2.0-84903841109 (Scopus ID)
Conference
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Note

QC 20140609

Available from: 2014-05-21 Created: 2014-05-21 Last updated: 2015-08-18Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-8072-1742

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