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Publications (10 of 92) Show all publications
de Medeiros, J. E. E., Ungureanu, G. & Sander, I. (2018). An Algebra for Modeling Continuous Time Systems. In: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE): . Paper presented at Design, Automation and Test in Europe Conference and Exhibition (DATE), MAR 19-23, 2018, Dresden, GERMANY (pp. 861-864). IEEE
Open this publication in new window or tab >>An Algebra for Modeling Continuous Time Systems
2018 (English)In: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), IEEE, 2018, p. 861-864Conference paper, Published paper (Refereed)
Abstract [en]

Advancements on analog integrated design have led to new possibilities for complex systems combining both continuous and discrete time modules on a signal processing chain. However, this also increases the complexity any design flow needs to address in order to describe a synergy between the two domains, as the interactions between them should be better understood. We believe that a common language for describing continuous and discrete time computations is beneficial for such a goal and a step towards it is to gain insight and describe more fundamental building blocks. In this work we present an algebra based on the General Purpose Analog Computer, a theoretical model of computation recently updated as a continuous time equivalent of the Turing Machine.

Place, publisher, year, edition, pages
IEEE, 2018
Series
Design Automation and Test in Europe Conference and Exhibition, ISSN 1530-1591
National Category
Computer Systems
Identifiers
urn:nbn:se:kth:diva-231648 (URN)10.23919/DATE.2018.8342126 (DOI)000435148800157 ()2-s2.0-85048803443 (Scopus ID)978-3-9819-2630-9 (ISBN)
Conference
Design, Automation and Test in Europe Conference and Exhibition (DATE), MAR 19-23, 2018, Dresden, GERMANY
Note

QC 20180905

QC 20181010

Available from: 2018-09-05 Created: 2018-09-05 Last updated: 2018-11-12Bibliographically approved
Ungureanu, G., de Medeiros, J. E. G. & Sander, I. (2018). Bridging Discrete and Continuous Time Models with Atoms. In: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE): . Paper presented at Design, Automation and Test in Europe Conference and Exhibition (DATE), MAR 19-23, 2018, Dresden, GERMANY (pp. 277-280). IEEE
Open this publication in new window or tab >>Bridging Discrete and Continuous Time Models with Atoms
2018 (English)In: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), IEEE , 2018, p. 277-280Conference paper, Published paper (Refereed)
Abstract [en]

Recent trends in replacing traditionally digital components with analog counterparts in order to overcome physical limitations have led to an increasing need for rigorous modeling and simulation of hybrid systems. Combining the two domains under the same set of semantics is not straightforward and often leads to chaotic and non-deterministic behavior due to the lack of a common understanding of aspects concerning time. We propose an algebra of primitive interactions between continuous and discrete aspects of systems which enables their description within two orthogonal layers of computation. We show its benefits from the perspective of modeling and simulation, through the example of an RC oscillator modeled in a formal framework implementing this algebra.

Place, publisher, year, edition, pages
IEEE, 2018
Series
Design Automation and Test in Europe Conference and Exhibition, ISSN 1530-1591
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-231647 (URN)000435148800050 ()2-s2.0-85048869050 (Scopus ID)978-3-9819-2630-9 (ISBN)
Conference
Design, Automation and Test in Europe Conference and Exhibition (DATE), MAR 19-23, 2018, Dresden, GERMANY
Note

QC 20180904

Available from: 2018-09-04 Created: 2018-09-04 Last updated: 2018-09-26Bibliographically approved
Rosvall, K., Mohammadat, T., Ungureanu, G., Öberg, J. & Sander, I. (2018). Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors. In: : . Paper presented at 2018 21st Euromicro Conference on Digital System Design (DSD).
Open this publication in new window or tab >>Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors
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2018 (English)Conference paper, Published paper (Refereed)
Abstract [en]

System level optimization for multiple mixed-criticality applications on shared networked multiprocessor platforms is extremely challenging. Substantial complexity arises from the interdependence between the multiple subproblems of mapping, scheduling and platform configuration under the consideration of several, potentially orthogonal, performance metrics and constraints. Instead of using heuristic algorithms and problem decomposition, novel unified design space exploration (DSE) approaches based on Constraint Programming (CP) have in the recent years shown promising results. The work in this paper takes advantage of the modularity of CP models, in order to support heterogeneous multiprocessor Network-on-Chip (NoC) with Temporally Disjoint Networks (TDNs) aware message injection. The DSE supports a range of design criteria, in particular the optimization and satisfaction of power and throughput. In addition, the DSE now provides a valid configuration for the TDNs that guarantees the performance required to fulfil the design goals. The experiments show the capability of the approach to find low-power and high-throughput designs, and validate a resulting design on a physical TDN-based NoC implementation.

National Category
Engineering and Technology Electrical Engineering, Electronic Engineering, Information Engineering Embedded Systems Computer Systems
Identifiers
urn:nbn:se:kth:diva-239007 (URN)10.1109/DSD.2018.00011 (DOI)978-1-5386-7377-5 (ISBN)
Conference
2018 21st Euromicro Conference on Digital System Design (DSD)
Note

QC 20181114

Available from: 2018-11-14 Created: 2018-11-14 Last updated: 2018-11-20Bibliographically approved
Rosvall, K. & Sander, I. (2018). Flexible and Tradeoff-Aware Constraint-Based Design Space Exploration for Streaming Applications on Heterogeneous Platforms. ACM Transactions on Design Automation of Electronic Systems, 23(2), Article ID 21.
Open this publication in new window or tab >>Flexible and Tradeoff-Aware Constraint-Based Design Space Exploration for Streaming Applications on Heterogeneous Platforms
2018 (English)In: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, E-ISSN 1557-7309, Vol. 23, no 2, article id 21Article in journal (Refereed) Published
Abstract [en]

Due to its complexity, the problem of mapping and scheduling streaming applications on heterogeneous MPSoCs under real-time and performance constraints has traditionally been tackled by incomplete heuristic algorithms. In recent years, approaches based on Constraint Programming (CP) have shown promising results as complete methods for finding optimal mappings, in particular concerning throughput. However, so far none of the available CP approaches consider the tradeoff between throughput and buffer requirements or throughput and power consumption. This article integrates tradeoff awareness into the CP model and introduces a two-step solving approach that utilizes the advantages of heuristics, while still keeping the completeness property of CP. With a number of experiments considering several streaming applications and different platform models, the article illustrates not only the efficiency of the presented model but also its suitability for solving different problems with various combinations of performance constraints.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2018
Keywords
Constraint programming, correct-by-construction, design space exploration, performance analysis
National Category
Control Engineering
Identifiers
urn:nbn:se:kth:diva-222443 (URN)10.1145/3133210 (DOI)000423468900009 ()
Note

QC 20180219

Available from: 2018-02-19 Created: 2018-02-19 Last updated: 2018-05-24Bibliographically approved
Khalilzad, N., Rosvall, K. & Sander, I. (2017). A modular design space exploration framework for multiprocessor real-time systems. In: Forum on Specification and Design Languages: . Paper presented at 2016 Forum on Specification and Design Languages, FDL 2016, 14 September 2016 through 16 September 2016. IEEE, Article ID 7880377.
Open this publication in new window or tab >>A modular design space exploration framework for multiprocessor real-time systems
2017 (English)In: Forum on Specification and Design Languages, IEEE, 2017, article id 7880377Conference paper, Published paper (Refereed)
Abstract [en]

Embedded system designers often face a large number of design alternatives when designing complex systems. A designer must select an alternative which satisfies application constraints (e.g. timing requirements) while optimizing system level objectives such as overall energy consumption. The size of design space is often very large giving rise to the need for systematic Design Space Exploration (DSE) methods. In this paper we address the DSE problem for real-time applications that belong to two different domains: (i) streaming applications modeled using the synchronous dataflow graphs; (ii) feedback control tasks modeled using the periodic task model. We consider a heterogeneous multiprocessor platform in which processors communicate through a predictable bus architecture. We present our DSE tool in which the DSE problem is modeled as a constraint satisfaction problem, and it is solved using a constraint programming solver. This approach provides a modular framework in which different constraints such as deadline, throughput and energy consumption can easily be plugged depending on the system being designed.

Place, publisher, year, edition, pages
IEEE, 2017
Keywords
Constraint Programming, Design Space Exploration, Multiprocessors, Periodic Tasks, Real-Time Systems, Synchronous Dataflow, Computer programming, Constraint satisfaction problems, Constraint theory, Data flow analysis, Embedded systems, Energy utilization, Interactive computer systems, Multiprocessing systems, Specifications, Real time systems
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-210144 (URN)10.1109/FDL.2016.7880377 (DOI)2-s2.0-85017111938 (Scopus ID)9791092279177 (ISBN)
Conference
2016 Forum on Specification and Design Languages, FDL 2016, 14 September 2016 through 16 September 2016
Note

QC 20170630

Available from: 2017-06-30 Created: 2017-06-30 Last updated: 2017-06-30Bibliographically approved
Grüttner, K., Görgen, R., Schreiner, S., Herrera, F., Peñil, P., Medina, J., . . . Quaglia, D. (2017). CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties. Microprocessors and microsystems, 51, 39-55
Open this publication in new window or tab >>CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties
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2017 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 51, p. 39-55Article in journal (Refereed) Published
Abstract [en]

The increasing processing power of today's HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels. This article presents an overview of the CONTREX European project, its main innovative technology (extension of a model based design approach, functional and extra-functional analysis with executable models and run-time management) and the final results of three industrial use-cases from different domain (avionics, automotive and telecommunication).

Place, publisher, year, edition, pages
Elsevier B.V., 2017
Keywords
Criticality (nuclear fission), Energy efficiency, Project management, Computing resource, Extra-functional properties, Industrial use case, Innovative technology, Mixed criticalities, Model-based design approaches, Segregation mechanism, Timing constraints, Embedded systems
National Category
Computer Sciences
Identifiers
urn:nbn:se:kth:diva-216480 (URN)10.1016/j.micpro.2017.03.012 (DOI)000404710100004 ()2-s2.0-85018492812 (Scopus ID)
Note

QC 20171201

Available from: 2017-12-01 Created: 2017-12-01 Last updated: 2018-01-13Bibliographically approved
Sander, I., Jantsch, A. & Attarzadeh-Niaki, S.-H. -. (2017). ForSyDe: System design using a functional language and models of computation. In: Handbook of Hardware/Software Codesign: (pp. 99-140). Springer Netherlands
Open this publication in new window or tab >>ForSyDe: System design using a functional language and models of computation
2017 (English)In: Handbook of Hardware/Software Codesign, Springer Netherlands, 2017, p. 99-140Chapter in book (Other academic)
Abstract [en]

The ForSyDe methodology aims to push system design to a higher level of abstraction by combining the functional programming paradigm with the theory of Models of Computation (MoCs). A key concept of ForSyDe is the use of higher-order functions as process constructors to create processes. This leads to well-defined and well-structured ForSyDe models and gives a solid base for formal analysis. The book chapter introduces the basic concepts of the ForSyDe modeling framework and presents libraries for several MoCs and MoC interfaces for the modeling of heterogeneous systems, including support for the modeling of run-time reconfigurable processes. The formal nature of ForSyDe enables transformational design refinement using both semantic-preserving and nonsemantic-preserving design transformations. The chapter also introduces a general synthesis concept based on process constructors, which is exemplified by means of a hardware synthesis tool for synchronous ForSyDe models. Most examples in the chapter are modeled with the Haskell version of ForSyDe. However, to illustrate that ForSyDe is languageindependent, the chapter also contains a short overview of SystemC-ForSyDe.

Place, publisher, year, edition, pages
Springer Netherlands, 2017
National Category
Computer Systems
Identifiers
urn:nbn:se:kth:diva-219645 (URN)10.1007/978-94-017-7267-9_5 (DOI)2-s2.0-85035344114 (Scopus ID)9789401772679 (ISBN)9789401772662 (ISBN)
Note

QC 20171212

Available from: 2017-12-12 Created: 2017-12-12 Last updated: 2017-12-12Bibliographically approved
Attarzadeh-Niaki, S.-H. -., Altinel, E., Koedam, M., Molnos, A., Sander, I. & Goossens, K. (2016). A composable and predictable MPSoC design flow for multiple real-time applications. In: Model-Implementation Fidelity in Cyber Physical System Design: (pp. 157-174). Springer International Publishing
Open this publication in new window or tab >>A composable and predictable MPSoC design flow for multiple real-time applications
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2016 (English)In: Model-Implementation Fidelity in Cyber Physical System Design, Springer International Publishing , 2016, p. 157-174Chapter in book (Other academic)
Abstract [en]

Design of real-time MPSoC systems including multiple applications is challenging because temporal requirements of each application must be respected throughout the entire design flow. Currently the design of different applications is often interdependent, making converge to a solution for each application difficult. This chapter proposes a compositional method to design applications independently, and then to execute them without interference. We define a formal modeling framework as a suitable entry point for application design. The models are executable, which enables early detection of specification errors, and include the formal properties of the applications based on well-defined models of computation. We combine this with a predictable MPSoC platform template that has a supporting design flow but lacks a simulation front-end. The structure and behavior of the application models are exported to an intermediate format via introspection which is iteratively transformed for the backend flow. We identify the problems arising in this transformation and provide appropriate solutions. The design flow is demonstrated by a system consisting of two streaming applications where less than half of the design time is dedicated to operating on the integrated system model.

Place, publisher, year, edition, pages
Springer International Publishing, 2016
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-216879 (URN)10.1007/978-3-319-47307-9_5 (DOI)2-s2.0-85029086803 (Scopus ID)9783319473079 (ISBN)9783319473062 (ISBN)
Note

Export Date: 24 October 2017; Book Chapter; Correspondence Address: Attarzadeh-Niaki, S.-H.; Shahid Beheshti UniversityIran; email: h_attarzadeh@sbu.ac.ir. QC 20171128

Available from: 2017-11-28 Created: 2017-11-28 Last updated: 2017-11-28Bibliographically approved
Lenz, A., Blazquez, M.-A. A., Coronel, J., Crespo, A., Davidmann, S., Diaz Garcia, J. C., . . . Soederquist, I. (2016). SAFEPOWER project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems. In: 19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016): . Paper presented at 19th Euromicro Conference on Digital System Design (DSD), AUG 31-SEP 02, 2016, Limassol, CYPRUS (pp. 294-300). IEEE
Open this publication in new window or tab >>SAFEPOWER project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems
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2016 (English)In: 19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016), IEEE, 2016, p. 294-300Conference paper, Published paper (Refereed)
Abstract [en]

With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible not regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised, because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER(1) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This paper will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.

Place, publisher, year, edition, pages
IEEE, 2016
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-197007 (URN)10.1109/DSD.2016.64 (DOI)000386638800039 ()978-1-5090-2816-0 (ISBN)
Conference
19th Euromicro Conference on Digital System Design (DSD), AUG 31-SEP 02, 2016, Limassol, CYPRUS
Note

QC 20161212

Available from: 2016-12-12 Created: 2016-11-28 Last updated: 2016-12-12Bibliographically approved
Hjort Blindell, G., Menne, C. & Sander, I. (2016). Synthesizing Code for GPGPUs from abstract formal models. In: 16th Conference on Languages, Design Methods, and Tools for Electronic System Design, FDL 2014: . Paper presented at 14 October 2014 through 16 October 2014 (pp. 115-134). Springer
Open this publication in new window or tab >>Synthesizing Code for GPGPUs from abstract formal models
2016 (English)In: 16th Conference on Languages, Design Methods, and Tools for Electronic System Design, FDL 2014, Springer, 2016, p. 115-134Conference paper, Published paper (Refereed)
Abstract [en]

Today multiple frameworks exist for elevating the task of writing programs for GPGPUs, which are massively data-parallel execution platforms. These are needed as writing correct and high-performing applications for GPGPUs is notoriously difficult due to the intricacies of the underlying architecture. However, the existing frameworks lack a formal foundation that makes them difficult to use together with formal verification, testing, and design space exploration. We present in this chapter a novel software synthesis tool—called f2cc—which is capable of generating efficient GPGPU code from abstract formal models based on the synchronous model of computation. These models can be built using high-level modeling methodologies that hide low-level architecture details from the developer. The correctness of the tool has been experimentally validated on models derived from two applications. The experiments also demonstrate that the synthesized GPGPU code yielded a 28× speedup when executed on a graphics card with 96 cores and compared against a sequential version that uses only the CPU.

Place, publisher, year, edition, pages
Springer, 2016
Keywords
Architectural design, Codes (symbols), Computational linguistics, Program processors, Systems analysis, Design space exploration, Formal foundation, Graphics card, High-level modeling, High-performing applications, Software synthesis, Synchronous models, Writing projects, Design
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-181119 (URN)10.1007/978-3-319-24457-0_7 (DOI)2-s2.0-84952775263 (Scopus ID)9783319244556 (ISBN)
Conference
14 October 2014 through 16 October 2014
Note

QC 20160209

Available from: 2016-02-09 Created: 2016-01-29 Last updated: 2016-02-09Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0003-4859-3100

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