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Hellström, Per-ErikORCID iD iconorcid.org/0000-0001-6705-1660
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Publications (10 of 129) Show all publications
Hou, S., Hellström, P.-E., Zetterling, C.-M. & Östling, M. (2019). A 4H-SiC BJT as a Switch for On-Chip Integrated UV Photodiode. IEEE Electron Device Letters, 40(1), 51-54
Open this publication in new window or tab >>A 4H-SiC BJT as a Switch for On-Chip Integrated UV Photodiode
2019 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 40, no 1, p. 51-54Article in journal (Refereed) Published
Abstract [en]

This letter presents the design, fabrication, and characterization of a 4H-SiC n-p-n bipolar junction transistor as a switch controlling an on-chip integrated p-i-n photodiode. The transistor and photodiode share the same epitaxial layers and topside contacts for each terminal. By connecting the collector of the transistor and the anode of the photodiode, the photo current from the photodiode is switched off at low base voltage (cutoff region of the transistor) and switched on at high base voltage (saturation region of the transistor). The transfer voltage of the circuit decreases as the ambient temperature increases (2 mV/degrees C). Both the on-state and off-state current of the circuit have a positive temperature coefficient and the on/off ratio is >80 at temperature ranged from 25 degrees C to 400 degrees C. It is proposed that the on/off ratio can be increased by similar to 1000 times by adding a light blocking layer on the transistor to reduce light induced off-state current in the circuit.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2019
Keywords
4H-SiC, BJT, UV, photodiode, high temperature, switch
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-242990 (URN)10.1109/LED.2018.2883749 (DOI)000456172600013 ()2-s2.0-85057777289 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation
Note

QC 20190204

Available from: 2019-02-04 Created: 2019-02-04 Last updated: 2019-04-10Bibliographically approved
Chaourani, P., Rodriguez, S., Hellström, P.-E. & Rusu, A. (2019). Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 27(2), 468-480
Open this publication in new window or tab >>Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines
2019 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, no 2, p. 468-480Article in journal (Refereed) Published
Abstract [en]

Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2019
Keywords
Area reduction, inductors, monolithic 3-D (M3D) radio-frequency/analog-mixed signal (RF/AMS) circuits, M3D integration, shielding
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-244530 (URN)10.1109/TVLSI.2018.2877132 (DOI)000458069300018 ()2-s2.0-85056564540 (Scopus ID)
Note

QC 20190403

Available from: 2019-04-03 Created: 2019-04-03 Last updated: 2019-05-22Bibliographically approved
Hou, S., Shakir, M., Hellström, P.-E., Zetterling, C.-M. & Östling, M. (2019). Process Control and Optimization of 4H-SiC Semiconductor Devices and Circuits. In: Proceedings of the 3rd Electron Devices Technology and Manufacturing, (EDTM) Conference 2019: . Paper presented at The 3rd Electron Devices Technology and Manufacturing (EDTM) Conference. IEEE
Open this publication in new window or tab >>Process Control and Optimization of 4H-SiC Semiconductor Devices and Circuits
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2019 (English)In: Proceedings of the 3rd Electron Devices Technology and Manufacturing, (EDTM) Conference 2019, IEEE, 2019Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
IEEE, 2019
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-248421 (URN)
Conference
The 3rd Electron Devices Technology and Manufacturing (EDTM) Conference
Note

QC 20190411

Available from: 2019-04-08 Created: 2019-04-08 Last updated: 2019-04-11Bibliographically approved
Jayakumar, G., Hellström, P.-E. & Östling, M. (2019). Utilizing the superior etch stop quality of HfO 2 in the front end of line wafer scale integration of silicon nanowire biosensors. Microelectronic Engineering, 212, 13-20
Open this publication in new window or tab >>Utilizing the superior etch stop quality of HfO 2 in the front end of line wafer scale integration of silicon nanowire biosensors
2019 (English)In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 212, p. 13-20Article in journal (Refereed) Published
Abstract [en]

Silicon nanowire (SiNW) biosensors have received a special attention from the research community due to its ability to detect a range of species. The nano feature size of the SiNW has been exploited to fabricate small, low-cost, robust, portable, real-time read-out biosensors. These sensors are manufactured by two methods – top-down or bottom-up. Instead of the bottom-up method, the top-down approach is widely used due to its compatibility with complementary metal-oxide semiconductor (CMOS) process and scope of mass production. However, in the top-down method, the post fabrication microfluidic channel integration to access the SiNW test site remains complex and challenging. Since the nanosensor is expected to operate in a bio environment, it is essential to passivate the metal electrodes while pathways have to be made to access the test site. In this paper, we present a relatively easier method to access the SiNW test site without employing complex microfluidic channels while achieving leakage free passivation of metal electrodes and preserving the integrity of the nanosensor. This is accomplished in the last step of the manufacturing process by employing a lithography mask and reactive ion etching (RIE). HfO 2 integrated crystalline silicon nanosensors are manufactured using novel top-down front end of line (FEOL) sidewall transfer lithography (STL) process. HfO 2 acts as an etch stop layer while performing RIE in the last step to access the sensor test site. The 100 mm wafer scale results of 20 nm × 60 nm × 6 μm (H x W x L) p-type nanosensors shows an average I on /I off ≥ 10 5 with maximum turn-on voltage of −4 V and uniform subthreshold slope of 70 mV/dec. In comparison with sensors encapsulated with SiO 2 , the HfO 2 integrated nanosensors were found to improve the threshold voltage variation by 50%. Based on this work, the HfO 2 integrated SiNW demonstrates good stability for biosensing application.

Place, publisher, year, edition, pages
Elsevier B.V., 2019
Keywords
Biosensor, CMOS compatible, FEOL, HfO 2, LOC, Silicon nanowire access, Biosensors, CMOS integrated circuits, Electrodes, Fluidic devices, Hafnium oxides, Lithography, Metals, Microfluidics, MOS devices, Nanosensors, Nanowires, Oxide semiconductors, Reactive ion etching, Silica, Silicon oxides, Silicon wafers, Threshold voltage, WSI circuits, Biosensing applications, Complementary metal oxide semiconductor process, HfO2, Manufacturing process, Silicon nanowires, Threshold voltage variation, Nitrogen compounds
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-252476 (URN)10.1016/j.mee.2019.03.006 (DOI)000468708700003 ()2-s2.0-85063917094 (Scopus ID)
Note

QC 20190715

Available from: 2019-07-15 Created: 2019-07-15 Last updated: 2019-07-15Bibliographically approved
Jayakumar, G., Legallais, M., Hellström, P.-E., Mouis, M., Pignot-Paintrand, I., Stambouli, V., . . . Östling, M. (2019). Wafer-scale HfO 2 encapsulated silicon nanowire field effect transistor for efficient label-free DNA hybridization detection in dry environment. Nanotechnology, 30(18)
Open this publication in new window or tab >>Wafer-scale HfO 2 encapsulated silicon nanowire field effect transistor for efficient label-free DNA hybridization detection in dry environment
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2019 (English)In: Nanotechnology, ISSN 0957-4484, E-ISSN 1361-6528, Vol. 30, no 18Article in journal (Refereed) Published
Place, publisher, year, edition, pages
NLM (Medline), 2019
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-246421 (URN)10.1088/1361-6528/aaffa5 (DOI)30654356 (PubMedID)2-s2.0-85061994755 (Scopus ID)
Note

QC 20190329

Available from: 2019-03-29 Created: 2019-03-29 Last updated: 2019-03-29Bibliographically approved
Chaourani, P., Stathis, D., Rodriguez, S., Hellström, P.-E. & Rusu, A. (2018). A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors. In: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S): . Paper presented at IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE conference proceedings
Open this publication in new window or tab >>A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors
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2018 (English)In: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE conference proceedings, 2018Conference paper, Published paper (Refereed)
Abstract [en]

The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2018
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-235831 (URN)000462960700020 ()2-s2.0-85063138253 (Scopus ID)
Conference
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
Note

QC 20181008

Available from: 2018-10-06 Created: 2018-10-06 Last updated: 2019-07-31Bibliographically approved
Abedin, A., Zurauskaite, L., Asadollahi, A., Garidis, K., Jayakumar, G., Malm, B. G., . . . Östling, M. (2018). Germanium on Insulator Fabrication for Monolithic 3-D Integration. IEEE Journal of the Electron Devices Society, 6(1), 588-593
Open this publication in new window or tab >>Germanium on Insulator Fabrication for Monolithic 3-D Integration
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2018 (English)In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed) Published
Abstract [en]

A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018
Keywords
GOI, wafer bonding, selective etching, GOI MOSFET, 3D integration
National Category
Materials Chemistry
Identifiers
urn:nbn:se:kth:diva-231645 (URN)10.1109/JEDS.2018.2801335 (DOI)000435505000007 ()2-s2.0-85041650674 (Scopus ID)
Funder
Swedish Foundation for Strategic Research
Note

QC 20180904

Available from: 2018-09-04 Created: 2018-09-04 Last updated: 2018-10-19Bibliographically approved
Abedin, A., Zurauskaite, L., Asadollahi, A., Garidis, K., Jayakumar, G., Malm, B. G., . . . Östling, M. (2018). GOI fabrication for monolithic 3D integration. In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017: . Paper presented at 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Hyatt Regency San Francisco Airport Hotel Burlingame, United States, 16 October 2017 through 18 October 2017 (pp. 1-3). Institute of Electrical and Electronics Engineers (IEEE), 2018
Open this publication in new window or tab >>GOI fabrication for monolithic 3D integration
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2018 (English)In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper, Published paper (Refereed)
Abstract [en]

A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
3D Integration, GOI, GOI MOSFET, Selective Etching, Wafer Bonding
National Category
Other Engineering and Technologies
Identifiers
urn:nbn:se:kth:diva-230046 (URN)10.1109/S3S.2017.8309201 (DOI)2-s2.0-85047768082 (Scopus ID)9781538637654 (ISBN)
Conference
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Hyatt Regency San Francisco Airport Hotel Burlingame, United States, 16 October 2017 through 18 October 2017
Note

QC 20180611

Available from: 2018-06-11 Created: 2018-06-11 Last updated: 2018-06-11Bibliographically approved
Zurauskaite, L., Jones, L., Dhanak, V. R., Mitrovic, I. Z., Hellström, P.-E. & Östling, M. (2018). Investigation of Tm2Oj as a gate dielectric for Ge MOS devices. In: ECS Transactions: . Paper presented at 8th Symposium on SiGe, Ge, and Related Compounds: Materials, Processing, and Devices - AiMES 2018, ECS and SMEQ Joint International Meeting, 30 September 2018 through 4 October 2018 (pp. 67-73). Electrochemical Society, 86(7)
Open this publication in new window or tab >>Investigation of Tm2Oj as a gate dielectric for Ge MOS devices
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2018 (English)In: ECS Transactions, Electrochemical Society, 2018, Vol. 86, no 7, p. 67-73Conference paper, Published paper (Refereed)
Abstract [en]

In this work atomic layer deposited TnOj has been investigated as a high-k dielectric for Ge-based gate stacks. It is shown that when Tm203 is deposited on high-quality Ge/Ge02 gates, the interface state density of the gate stack is degraded. A series of post-deposition anneals are studied in order to improve the interface state density of Ge/GeO/TmjOs gates, and it is demonstrated that a rapid thermal anneal in O2 ambient can effectively reduce the interface state density to below 5-10" cmeV1 without increasing the equivalent oxide thickness. Fixed charge density in Ge/GeOx/Tm20j gates has also been investigated, and it is shown that while O2 post-deposition anneal improves the interface state density, the fixed charge density is degraded.

Place, publisher, year, edition, pages
Electrochemical Society, 2018
Series
ECS Transactions, ISSN 1938-6737 ; 86
National Category
Other Materials Engineering
Identifiers
urn:nbn:se:kth:diva-246529 (URN)10.1149/08607.0067ecst (DOI)2-s2.0-85058463674 (Scopus ID)9781607685395 (ISBN)
Conference
8th Symposium on SiGe, Ge, and Related Compounds: Materials, Processing, and Devices - AiMES 2018, ECS and SMEQ Joint International Meeting, 30 September 2018 through 4 October 2018
Note

QC 20190320

Available from: 2019-03-20 Created: 2019-03-20 Last updated: 2019-03-20Bibliographically approved
Jayakumar, G., Hellström, P.-E. & Östling, M. (2018). Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application. Micromachines, 9(11), Article ID 544.
Open this publication in new window or tab >>Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application
2018 (English)In: Micromachines, ISSN 2072-666X, E-ISSN 2072-666X, Vol. 9, no 11, article id 544Article in journal (Refereed) Published
Abstract [en]

Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (V-G) and backgate voltage (V-BG). The liquid potential can be monitored using the FG. We report the transfer characteristics (I-D-V-G) of N- and P-type SiRi pixels. Further, the I-D-V-G characteristics of the SiRis are studied at different V-BG. The application of V-BG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (V-TH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large V-BG (25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large V-BG to switch ON. Thus, P-type pixels exhibit excellent I-ON/I-OFF 10(6), SS of 70-80 mV/dec and V-TH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.

Place, publisher, year, edition, pages
MDPI, 2018
Keywords
silicon ribbon pixel, silicon ribbon biosensor, lab-on-chip, SiRi CMOS integration, selective multiplexed detection, SiRi frontgate mode, SiRi backgate mode
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-240004 (URN)10.3390/mi9110544 (DOI)000451314900007 ()2-s2.0-85055740494 (Scopus ID)
Note

QC 20181210

Available from: 2018-12-10 Created: 2018-12-10 Last updated: 2018-12-10Bibliographically approved
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ORCID iD: ORCID iD iconorcid.org/0000-0001-6705-1660

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