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Hussain, M. W., Elahipanah, H., Zumbro, J. E., Rodriguez, S., Malm, B. G., Mantooth, H. A. & Rusu, A. (2019). A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications. IEEE Journal of the Electron Devices Society, 7(1), 191-195
Open this publication in new window or tab >>A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications
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2019 (English)In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 7, no 1, p. 191-195Article in journal (Refereed) Published
Abstract [en]

This brief presents a 59.5 MHz negative resistanceoscillator for high-temperature operation. The oscillator employs an in-house 4H-SiC BJT, integrated with the requiredcircuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room-temperature up to 400 C. The oscillator delivers an output◦power of 11.2 dBm into a 50 Ω load at 25 C, which decreases to 8.4 dBm at 400 C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased witha collector current of 35 mA from a 12 V supply and has amaximum DC power consumption of 431 mW.

Keywords
4H-SiC BJT, high-temperature, LTCC, negative resistance, oscillator
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-245068 (URN)10.1109/JEDS.2018.2889638 (DOI)2-s2.0-85059455428 (Scopus ID)
Note

QC 20190311

Available from: 2019-03-05 Created: 2019-03-05 Last updated: 2019-04-24Bibliographically approved
Malm, B. G. (2019). Fact or Fiction? – Citation Categories and their Use Cases in Thesis Bibliographies at KTH. In: This work was presented at KTH Scholarship of teaching and learning (SoTL) March 29, 2019: . Paper presented at KTH Scholarship of teaching and learning (SoTL).
Open this publication in new window or tab >>Fact or Fiction? – Citation Categories and their Use Cases in Thesis Bibliographies at KTH
2019 (English)In: This work was presented at KTH Scholarship of teaching and learning (SoTL) March 29, 2019, 2019Conference paper, Oral presentation with published abstract (Refereed)
Abstract [en]

Background and purpose

 

Since the first level (bachelor) thesis was introduced at KTH in the degree programs students are exposed to scientific writing at an early stage in their education. A key element of scientific writing is an efficient use of citations i.e. references to published work in the area. From a teacher perspective many first level thesis reports showed poor quality in this respect. In order to be able to study this observation, from a quantitative or empirical point of view, development a well-defined scientific method was highly motivated.

 

Work done

 

In my work a method, based on so called content analysis, was proposed and used to study student behavior in first level thesis reports, regarding their use of citations. The objective was to look at categories of in-text citations and to find evidence, supporting a hypothesis, that student use of citations show distinct patterns. These patterns could reflect that they rely too much on facts and show too little evidence of learning, regarding synthesis from reliable and valid scientific sources, in their respective technical domain. The citation category method, proposed by me, starts from an a priori set of “use cases” or “in-text citation categories”. Based on these categories all citations could be coded for further statistical analysis.

 

 

Observations

 

The empirical results were based on nine first level (BS) reports. These were selected to represent programs at the different schools at KTH. A full search was done in DiVA for the time span June 2013- June 2015 and the selected reports are a random sampling of the 1300 reports, found in the in the database.

The results clearly points towards a use of citations, where “presenting a fact” is emphasized over most other use cases. The use of a citation to “introduce or discuss contrasting views” or “in support of an argument” is seldom observed. On the other hand, the bulk of the in-text citations are used to shape the background survey. In extreme cases the whole thesis structure is based on the ideas, found in the studied literature. Finally, it is found that the reliability and validity of sources is sometimes commented upon by the thesis authors.

 

Take-home message

 

As students are exposed to scientific writing for the first time they display a pattern of using citations mainly to present facts. They have not yet learned that citations have many other valid use cases such as introducing or discussing contrasting views. Students need training and exposure to scientific writing in order to develop and broaden their use of citations. A natural extension of my study would be at the second level since these students have more training in scientific writing.

 

 

 

Keywords
Content analysis, bachelor thesis
National Category
Learning
Research subject
Education and Communication in the Technological Sciences
Identifiers
urn:nbn:se:kth:diva-247980 (URN)
Conference
KTH Scholarship of teaching and learning (SoTL)
Note

QC 20190412

Available from: 2019-04-01 Created: 2019-04-01 Last updated: 2019-04-12Bibliographically approved
Ekström, M., Malm, B. G. & Zetterling, C.-M. (2019). High-Temperature Recessed Channel SiC CMOS Inverters and Ring Oscillators. IEEE Electron Device Letters, 40(5), 670-673
Open this publication in new window or tab >>High-Temperature Recessed Channel SiC CMOS Inverters and Ring Oscillators
2019 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 40, no 5, p. 670-673Article in journal (Refereed) Published
Abstract [en]

Digital electronics in SiC find use in high-temperature applications. The objective of this study was to fabricate SiC CMOS without using ion implantation. In this letter, we present a recessed channel CMOS process. Selective doping is achieved by etching epitaxial layers into mesas. A deposited SiO2-film, post-annealed at lowtemperature and re-oxidized in pyrogenic steam, is used as the gate oxide to produce a conformal gate oxide over the non-planar topography. PMOS, NMOS, inverters, and ring oscillators are characterized at 200 °C. The PMOS requires reduced threshold voltage in order to enable long term reliability. This result demonstrates that it is possible to fabricate SiC CMOS without ion implantation and by low-temperature processing.

Keywords
Inverter, recessed channel, ring oscillator (RO), silicon carbide (4H-SiC), static CMOS
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-250275 (URN)10.1109/LED.2019.2903184 (DOI)2-s2.0-85064992240 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation, Working on VenusSwedish Foundation for Strategic Research , CMP Lab
Note

QC 20190428

Available from: 2019-04-27 Created: 2019-04-27 Last updated: 2019-05-16Bibliographically approved
Shakir, M., Hou, S., Hedayati, R., Malm, B. G., Östling, M. & Zetterling, C.-M. (2019). Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications. Electronics, 8(5)
Open this publication in new window or tab >>Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications
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2019 (English)In: Electronics, ISSN 2079-9292,, Vol. 8, no 5Article in journal (Other academic) Published
Abstract [en]

A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta (β) and collector current (IC) variation of SiC devices as temperature increases. The PDK-based complex digital ICsdesign flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.

Keywords
Process Design Kit (PDK); bipolar logic gates; high temperature digital integrated circuits (ICs); transistor–transistor logic (TTL); SiC bipolar transistor; SiC VLSI Circuits
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-248424 (URN)10.3390/electronics8050496 (DOI)
Funder
Knut and Alice Wallenberg Foundation, Working on Venus
Note

QC 20190410

Available from: 2019-04-08 Created: 2019-04-08 Last updated: 2019-05-23Bibliographically approved
Hussain, M. W., Elahipanah, H., Zumbro, J. E., Schröder, S., Rodriguez, S., Malm, B. G., . . . Rusu, A. (2018). A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology. IEEE Electron Device Letters, 39(6), 855-858
Open this publication in new window or tab >>A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology
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2018 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 6, p. 855-858Article in journal (Refereed) Accepted
Abstract [en]

This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.

Place, publisher, year, edition, pages
IEEE Press, 2018
Keywords
4H-SiC BJTs, high-temperature, RF, mixer
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-228486 (URN)10.1109/LED.2018.2829628 (DOI)000437086800018 ()2-s2.0-85045754083 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation
Note

QC 20180601

Available from: 2018-05-25 Created: 2018-05-25 Last updated: 2019-04-24Bibliographically approved
Hussain, M. W., Elahipanah, H., Schröder, S., Rodriguez, S., Malm, B. G., Östling, M. & Rusu, A. (2018). An Intermediate Frequency Amplifier for High-Temperature Applications. IEEE Transactions on Electron Devices, 65(4), 1411-1418
Open this publication in new window or tab >>An Intermediate Frequency Amplifier for High-Temperature Applications
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2018 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 65, no 4, p. 1411-1418Article in journal (Refereed) Accepted
Abstract [en]

This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than-7 and-11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base-collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
4H-silicon carbide (4H-SiC) bipolar junction transistors (BJTs), high temperature, intermediate frequency (IF) amplifiers, matching networks
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-227642 (URN)10.1109/TED.2018.2804392 (DOI)000427856300022 ()2-s2.0-85042860667 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation
Note

QC 20180509

Available from: 2018-05-09 Created: 2018-05-09 Last updated: 2019-04-24Bibliographically approved
Abedin, A., Zurauskaite, L., Asadollahi, A., Garidis, K., Jayakumar, G., Malm, B. G., . . . Östling, M. (2018). Germanium on Insulator Fabrication for Monolithic 3-D Integration. IEEE Journal of the Electron Devices Society, 6(1), 588-593
Open this publication in new window or tab >>Germanium on Insulator Fabrication for Monolithic 3-D Integration
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2018 (English)In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed) Published
Abstract [en]

A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018
Keywords
GOI, wafer bonding, selective etching, GOI MOSFET, 3D integration
National Category
Materials Chemistry
Identifiers
urn:nbn:se:kth:diva-231645 (URN)10.1109/JEDS.2018.2801335 (DOI)000435505000007 ()2-s2.0-85041650674 (Scopus ID)
Funder
Swedish Foundation for Strategic Research
Note

QC 20180904

Available from: 2018-09-04 Created: 2018-09-04 Last updated: 2018-10-19Bibliographically approved
Hussain, M. W., Elahipanah, H., Rodriguez, S., Malm, B. G. & Rusu, A. (2018). Silicon Carbide BJT Oscillator Design Using S-Parameters. In: European Conference on Silicon Carbide and Related Materials (ECSCRM), Birmingham September 2-6, 2018.: . Paper presented at 12th European Conference on Silicon Carbide and Related Materials (ECSCRM), Birmingham September 2-6, 2018..
Open this publication in new window or tab >>Silicon Carbide BJT Oscillator Design Using S-Parameters
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2018 (English)In: European Conference on Silicon Carbide and Related Materials (ECSCRM), Birmingham September 2-6, 2018., 2018Conference paper, Poster (with or without abstract) (Refereed)
Abstract [en]

Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation isfurther aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, analternative small-signal, S-parameter based design method can be employed directly without goinginto complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 0C) was accessed by on-wafer probing and connectedby RF-cables to the rest of circuit passives, which were kept at room temperature (RT).

Keywords
RF oscillator, 4H-SiC BJT, S-parameters
National Category
Materials Engineering
Identifiers
urn:nbn:se:kth:diva-249685 (URN)
Conference
12th European Conference on Silicon Carbide and Related Materials (ECSCRM), Birmingham September 2-6, 2018.
Funder
Knut and Alice Wallenberg Foundation, 66167
Note

Accepted for publication in Materials Science Forum.

QC 20190507

Available from: 2019-04-17 Created: 2019-04-17 Last updated: 2019-05-07Bibliographically approved
Malm, B. G., Elahipanah, H., Salemi, A. & Östling, . (2017). Gated base structure for improved current gain in SiC bipolar technology. In: 2017 47th European Solid-State Device Research Conference (ESSDERC) 11-14 Sept. 2017: . Paper presented at 47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, 11 September 2017 through 14 September 2017 (pp. 122-125). Editions Frontieres
Open this publication in new window or tab >>Gated base structure for improved current gain in SiC bipolar technology
2017 (English)In: 2017 47th European Solid-State Device Research Conference (ESSDERC) 11-14 Sept. 2017, Editions Frontieres , 2017, p. 122-125Conference paper (Refereed)
Abstract [en]

Silicon Carbide (SiC) bipolar integrated circuits are a promising technology for extreme environment applications. SiC bipolar technology shows stable operation over a wide range of temperature. However, the current gain of the devices is suffering from high surface recombination, due to poor oxide passivation. In this paper we propose a gated base structure that offers improved current gain control. A polysilicon gate is formed on the passivation oxide on top of the base-link region. We investigate the current gain as a function of gate bias and temperature. A negative gate bias improves the gain at low collector current by more than 30% by suppressing the surface recombination. Measurements are presented at temperatures ranging from 300 K to 550 K and the gain is consistently improved. The proposed structure is also useful as a process monitor for the passivation oxide quality.

Place, publisher, year, edition, pages
Editions Frontieres, 2017
Series
European Solid-State Device Research Conference, ISSN 1930-8876
Keywords
bipolar, current gain, extreme enviroment, process monitor, silicon carbide (SiC), surface passivation, test structure
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-218127 (URN)10.1109/ESSDERC.2017.8066607 (DOI)2-s2.0-85033444950 (Scopus ID)9781509059782 (ISBN)
Conference
47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, 11 September 2017 through 14 September 2017
Note

QC 20171123

Available from: 2017-11-23 Created: 2017-11-23 Last updated: 2017-11-23Bibliographically approved
Banuazizi, S., Sani, S. R., Eklund, A., Naiini, M. M., Mohseni, S., Chung, S., . . . Åkerman, J. (2017). Order of magnitude improvement of nano-contact spin torque nano-oscillator performance. In: 2017 IEEE International Magnetics Conference, INTERMAG 2017: . Paper presented at 2017 IEEE International Magnetics Conference, INTERMAG 2017, Dublin, Ireland, 24 April 2017 through 28 April 2017. Institute of Electrical and Electronics Engineers (IEEE), Article ID 8007567.
Open this publication in new window or tab >>Order of magnitude improvement of nano-contact spin torque nano-oscillator performance
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2017 (English)In: 2017 IEEE International Magnetics Conference, INTERMAG 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, article id 8007567Conference paper, Published paper (Refereed)
Abstract [en]

Spin torque nano-oscillators [1,2] (STNO) represent a unique class of nano-scale microwave signal generators where spin transfer torque [3-5] (STT) from a direct spin-polarized current drives and controls the auto-oscillation of the local free layer magnetization, which through its oscillating magnetoresistance transforms the direct current into a tunable microwave voltage.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2017
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-223030 (URN)10.1109/INTMAG.2017.8007567 (DOI)2-s2.0-85034627173 (Scopus ID)9781538610862 (ISBN)
Conference
2017 IEEE International Magnetics Conference, INTERMAG 2017, Dublin, Ireland, 24 April 2017 through 28 April 2017
Note

QC 20180226

Available from: 2018-02-26 Created: 2018-02-26 Last updated: 2018-02-26Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0001-6459-749X

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