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BETA
Zetterling, Carl-MikaelORCID iD iconorcid.org/0000-0001-8108-2631
Alternative names
Publications (10 of 196) Show all publications
Kajihara, J., Kuroki, S.-I. -., Ishikawa, S., Maeda, T., Sezaki, H., Makino, T., . . . Zetterling, C.-M. (2018). 4H-SiC pMOSFETs with al-doped S/D and NbNi silicide ohmic contacts. In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017: . Paper presented at 17 September 2017 through 22 September 2017 (pp. 423-427). Trans Tech Publications
Open this publication in new window or tab >>4H-SiC pMOSFETs with al-doped S/D and NbNi silicide ohmic contacts
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2018 (English)In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, p. 423-427Conference paper, Published paper (Refereed)
Abstract [en]

4H-SiC pMOSFETs with Al-doped S/D and NbNi silicide ohmic contacts were demonstrated and were characterized at up to a temperature of 200°C. For the pMOSFETs, silicides on p-type 4H-SiC with Nb/Ni stack, Nb-Ni Alloy, Ni and Nb/Ti were investigated, and the Nb/Ni stack silicide with the contact resistance of 5.04×10-3 Ωcm2 were applied for the pMOSFETs.

Place, publisher, year, edition, pages
Trans Tech Publications, 2018
Keywords
4H-SiC, Harsh environment electronics, Nickel, Niobium, Ohmic contact, pMOSFET, Binary alloys, Electric contactors, MOSFET devices, Nickel alloys, Niobium alloys, Ohmic contacts, Silicides, Titanium alloys, Al doped, Harsh environment, Ni alloys, p-MOSFETs, P-type 4H-SiC, Silicon carbide
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-236375 (URN)10.4028/www.scientific.net/MSF.924.423 (DOI)2-s2.0-85049023373 (Scopus ID)9783035711455 (ISBN)
Conference
17 September 2017 through 22 September 2017
Note

QC 20181105

Available from: 2018-11-05 Created: 2018-11-05 Last updated: 2018-11-05Bibliographically approved
Kargarrazi, S., Elahipanah, H., Rodriguez, S. & Zetterling, C.-M. (2018). 500 °c, High Current Linear Voltage Regulator in 4H-SiC BJT Technology. IEEE Electron Device Letters, 39(4), 548-551
Open this publication in new window or tab >>500 °c, High Current Linear Voltage Regulator in 4H-SiC BJT Technology
2018 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 4, p. 548-551Article in journal (Refereed) Published
Abstract [en]

This letter reports on a fully integrated 2-linear voltage regulator operational in a wide temperature range from 25 °C up to 500 °C fabricated in 4H-SiC technology. The circuit provides a stable output voltage with less than 1% variation in the entire temperature range. This letter demonstrates the first power supply solution providing both high-temperature (up to 500 °C) and high-load driving capabilities (up to 2).

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
Bipolar junction transistor (BJT), high-temperature IC, linear voltage regulator (LVR), silicon carbide (SiC)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-227638 (URN)10.1109/LED.2018.2805229 (DOI)000428689000022 ()2-s2.0-85041829681 (Scopus ID)
Funder
Swedish Foundation for Strategic Research Knut and Alice Wallenberg Foundation
Note

QC 20180514

Available from: 2018-05-14 Created: 2018-05-14 Last updated: 2018-05-14Bibliographically approved
Kargarrazi, S., Elahipanah, H., Rodriguez, S. & Zetterling, C.-M. (2018). 500 degrees C, High Current Linear Voltage Regulator in 4H-SiC BJT Technology. IEEE Electron Device Letters, 39(4), 548-551
Open this publication in new window or tab >>500 degrees C, High Current Linear Voltage Regulator in 4H-SiC BJT Technology
2018 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 4, p. 548-551Article in journal (Refereed) Published
Abstract [en]

This letter reports on a fully integrated 2-A linear voltage regulator operational in a wide temperature range from 25 degrees C up to 500 degrees C fabricated in 4H-SiC technology. The circuit provides a stable output voltage with less than 1% variation in the entire temperature range. This letter demonstrates the first power supply solution providing both high-temperature (up to 500 degrees C) and high-load driving capabilities (up to 2 A).

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018
Keywords
Bipolar junction transistor (BJT), high-temperature IC, linear voltage regulator (LVR), silicon carbide (SiC)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-226194 (URN)10.1109/LED.2018.2805229 (DOI)000428689000022 ()2-s2.0-85041829681 (Scopus ID)
Note

QC 20180518

Available from: 2018-05-18 Created: 2018-05-18 Last updated: 2018-05-18Bibliographically approved
Shakir, M., Hou, S., Malm, B. G., Östling, M. & Zetterling, C.-M. (2018). A 600 degrees C TTL-Based 11-Stage Ring Oscillator in Bipolar Silicon Carbide Technology. IEEE Electron Device Letters, 39(10), 1540-1543
Open this publication in new window or tab >>A 600 degrees C TTL-Based 11-Stage Ring Oscillator in Bipolar Silicon Carbide Technology
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2018 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 10, p. 1540-1543Article in journal (Refereed) Published
Abstract [en]

Ring oscillators (ROs) are used to study the high-temperature characteristics of an in-house silicon carbide (SiC) technology. Design and successful operation of the in-house-fabricated 4H-SiC n-p-n bipolar transistors and TTL inverter-based 11-stage RO are reported from 25 degrees C to 600 degrees C. Non-monotonous temperature dependence was observed for the oscillator frequency; in the range of 25 degrees C to 300 degrees C, it increased with the temperature (1.33 MHz at 300 degrees C and V-CC = 15 V), while it decreased in the range of 300 degrees C-600 degrees C. The oscillator output frequency and delay were also characterized over a wide range of supply voltage (10 to 20 V). The noise margins of the TTL inverter were also measured; noise margin low (NML) decreases with the temperature, whereas noise margin high (NMH) increases with the temperature. The measured power-delay product (P-D . T-P) of the TTL inverter and 11-stage RO was approximate to 4.5 and approximate to 285 nJ, respectively, at V-CC= 15 V. Reliability testing indicated that the RO frequency of oscillation decreased 16% after HT characterization.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
Ring oscillator, TTL gates, Bipolar SiC gates, high temperature digital integrated circuits (ICs), transistor-transistor logic, silicon carbide electronics
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-237111 (URN)10.1109/LED.2018.2864338 (DOI)000446449300014 ()2-s2.0-85050029554 (Scopus ID)
Note

QC 20181120

Available from: 2018-11-20 Created: 2018-11-20 Last updated: 2018-11-20Bibliographically approved
Salemi, A., Elahipanah, H., Zetterling, C.-M. & Östling, M. (2018). Conductivity modulated and implantation-free 4H-SiC ultra-high-voltage PiN Diodes. In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017: . Paper presented at 17 September 2017 through 22 September 2017 (pp. 568-572). Trans Tech Publications Inc.
Open this publication in new window or tab >>Conductivity modulated and implantation-free 4H-SiC ultra-high-voltage PiN Diodes
2018 (English)In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications Inc., 2018, p. 568-572Conference paper, Published paper (Refereed)
Abstract [en]

Implantation-free mesa etched ultra-high-voltage 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. The diode’s design allows a high breakdown voltage of about 19.3 kV according to simulations. No reverse breakdown is observed up to 13 kV with a very low leakage current of 0.1 μA. A forward voltage drop (VF) and differential on-resistance (Diff. Ron) of 9.1 V and 41.4 mΩ cm2 are measured at 100 A/cm2, respectively, indicating the effect of conductivity modulation.

Place, publisher, year, edition, pages
Trans Tech Publications Inc., 2018
Keywords
4H-SiC PiN diode, Conductivity modulation, Differential on-resistance, Forward voltage drop, Implantation-free, Ultra-high-voltage, Diodes, Heterojunction bipolar transistors, Leakage currents, Modulation, Nitrogen compounds, Semiconductor junctions, Silicon carbide, Forward voltage drops, On-resistance, SiC PiN diodes, Ultra high voltage, Power semiconductor diodes
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-236358 (URN)10.4028/www.scientific.net/MSF.924.568 (DOI)2-s2.0-85049010479 (Scopus ID)9783035711455 (ISBN)
Conference
17 September 2017 through 22 September 2017
Note

QC 20181106

Available from: 2018-11-06 Created: 2018-11-06 Last updated: 2018-11-06Bibliographically approved
Shakir, M., Elahipanah, H., Hedayati, R. & Zetterling, C.-M. (2018). Electrical characterization of integrated 2-input TTL NAND Gate at elevated temperature, fabricated in bipolar SiC-technology. In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017: . Paper presented at International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Columbia, United States, 17 September 2017 through 22 September 2017 (pp. 958-961). Trans Tech Publications Inc., 924
Open this publication in new window or tab >>Electrical characterization of integrated 2-input TTL NAND Gate at elevated temperature, fabricated in bipolar SiC-technology
2018 (English)In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications Inc., 2018, Vol. 924, p. 958-961Conference paper, Published paper (Refereed)
Abstract [en]

This work presents the design and electrical characterization of in-house-fabricated 2-input NAND gate. The monolithic bipolar 2-input NAND gate employing transistor-transistor logic (TTL) is demonstrated in 4H-SiC and operates over a wide range of temperature and supply voltage. The fabricated circuit was characterized on the wafer by using a hot-chuck probe-station from 25 °C up to 500 °C. The circuit is also characterized over a wide range of voltage supply i.e. 11 to 20 V. The output-noise margin high (NMH) and output-noise margin low (NML) are also measured over a wide range of temperatures and supply voltages using voltage transfer characteristics (VTC). The transient response was measured by applying two square waves of, 5 kHz and 10 kHz. It is demonstrated that the dynamic parameters of the circuit are temperature dependent. The 2-input TTL NAND gate consumes 20 mW at 500 °C and 15 V.

Place, publisher, year, edition, pages
Trans Tech Publications Inc., 2018
Series
Materials Science Forum, ISSN 0255-5476 ; 924
Keywords
Bipolar junction transistor (BJT), Bipolar SiC NAND gate, Digital gate, High temperature integrated circuits (ICs), SiC ICs, Transistor-transistor logic (TTL), TTL NAND gate
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-238378 (URN)10.4028/www.scientific.net/MSF.924.958 (DOI)2-s2.0-85049001714 (Scopus ID)9783035711455 (ISBN)
Conference
International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Columbia, United States, 17 September 2017 through 22 September 2017
Note

QC 20181101

Available from: 2018-11-01 Created: 2018-11-01 Last updated: 2018-11-01Bibliographically approved
Ekström, M., Hou, S., Elahipanah, H., Salemi, A., Östling, M. & Zetterling, C.-M. (2018). Low temperature Ni-Al ohmic contacts to p-TYPE 4H-SiC using semi-salicide processing. In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017: . Paper presented at International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Columbia, United States, 17 September 2017 through 22 September 2017 (pp. 389-392). Trans Tech Publications, 924
Open this publication in new window or tab >>Low temperature Ni-Al ohmic contacts to p-TYPE 4H-SiC using semi-salicide processing
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2018 (English)In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, Vol. 924, p. 389-392Conference paper, Published paper (Refereed)
Abstract [en]

Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10-4 Ω cm2) to epitaxially grown p-type (>5×1018 cm-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni2Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.

Place, publisher, year, edition, pages
Trans Tech Publications, 2018
Series
Materials Science Forum, ISSN 0255-5476 ; 924
Keywords
Ni-Al, P-type ohmic contact, Rapid thermal processing (RTP), Silicon carbide (4H-SiC), Transfer length method (TLM)
National Category
Other Engineering and Technologies
Identifiers
urn:nbn:se:kth:diva-238393 (URN)10.4028/www.scientific.net/MSF.924.389 (DOI)2-s2.0-85049019579 (Scopus ID)9783035711455 (ISBN)
Conference
International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Columbia, United States, 17 September 2017 through 22 September 2017
Note

QC 20181108

Available from: 2018-11-08 Created: 2018-11-08 Last updated: 2018-11-08Bibliographically approved
Kurose, T., Kuroki, S.-I. -., Ishikawa, S., Maeda, T., Sezaki, H., Makino, T., . . . Zetterling, C.-M. (2018). Low-parasitic-capacitance self-aligned 4H-SiC nMOSFETs for harsh environment electronics. Materials Science Forum, 924, 971-974
Open this publication in new window or tab >>Low-parasitic-capacitance self-aligned 4H-SiC nMOSFETs for harsh environment electronics
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2018 (English)In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 924, p. 971-974Article in journal (Refereed) Published
Abstract [en]

Low-parasitic-capacitance 4H-SiC nMOSFETs using a novel self-aligned process were suggested and demonstrated. In these nMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain, drain-source capacitance) were investigated and low parasitic capacitance was achieved by the self-aligned structure

Place, publisher, year, edition, pages
Trans Tech Publications, 2018
Keywords
Harsh environment electronics, Self-aligned Process, SiC nMOSFET, Capacitance, Electric breakdown, MOSFET devices, Silicon carbide, Device characteristics, Drain sources, Harsh environment, Low-parasitic, NMOSFET, Parasitic capacitance, Self aligned process, Self aligned structure, Fluorine compounds
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-236430 (URN)10.4028/www.scientific.net/MSF.924.971 (DOI)2-s2.0-85049049901 (Scopus ID)9783035711455 (ISBN)
Note

QC 20181025

Available from: 2018-10-25 Created: 2018-10-25 Last updated: 2018-10-25Bibliographically approved
Hou, S., Hellström, P.-E., Zetterling, C.-M. & Östling, M. (2018). Scaling and modeling of high temperature 4H-SiC p-i-n photodiodes. IEEE Journal of the Electron Devices Society, 6(1), 139-145, Article ID 8240922.
Open this publication in new window or tab >>Scaling and modeling of high temperature 4H-SiC p-i-n photodiodes
2018 (English)In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 139-145, article id 8240922Article in journal (Refereed) Published
Abstract [en]

4H-SiC p-i-n photodiodes with various mesa areas (40,000μm2, 2500μm2, 1600μm2, and 400μm2) have been fabricated. Both C-V and I-V characteristics of the photodiodes have been measured at room temperature, 200 °C, 400 °C, and 500 °C. The capacitance and photo current (at 365 nm) of the photodiodes are directly proportional to the area. However, the dark current density increases as the device is scaled down due to the perimeter surface recombination effect. The photo to dark current ratio at the full depletion voltage of the intrinsic layer (-2.7 V) of the photodiode at 500 °C decreases 7 times as the size of the photodiode scales down 100 times. The static and dynamic behavior of the photodiodes are modeled with SPICE parameters at the four temperatures.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2018
Keywords
4H-SiC, high temperature, photodiode, scaling, Capacitance, Photodiodes, Silicon carbide, Dark current ratio, Full-depletion voltage, IV characteristics, Static and dynamic behaviors, Surface recombinations, Silicon compounds
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-223196 (URN)10.1109/JEDS.2017.2785618 (DOI)000423582900022 ()2-s2.0-85040046747 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation
Note

Export Date: 13 February 2018; Article; Correspondence Address: Hou, S.; School of Information and Communication Technology, KTH Royal Institute of TechnologySweden; email: shuoben@kth.se; Funding details: Knut och Alice Wallenbergs Stiftelse; Funding details: KTH, Kungliga Tekniska Högskolan. QC 20180228

Available from: 2018-02-28 Created: 2018-02-28 Last updated: 2018-02-28Bibliographically approved
Salemi, A., Elahipanah, H., Zetterling, C.-M. & Östling, M. (2017). 10+ kV implantation-free 4H-SiC PiN diodes. In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016: . Paper presented at 25 September 2016 through 29 September 2016 (pp. 423-426). Trans Tech Publications Ltd
Open this publication in new window or tab >>10+ kV implantation-free 4H-SiC PiN diodes
2017 (English)In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016, Trans Tech Publications Ltd , 2017, p. 423-426Conference paper (Refereed)
Abstract [en]

Implantation-free mesa etched 10+ kV 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. An area-optimized junction termination extension (O-JTE) is implemented in order to achieve a high breakdown voltage. The diodes design allows a high breakdown voltage of about 19.3 kV according to simulations by Sentaurus TCAD. No breakdown voltage is recorded up to 10 kV with a very low leakage current of 0.1 μA. The current spreading within the thick drift layer is considered and a voltage drop (VF) of 8.3 V and 11.4 V are measured at 50 A/cm2 and 100 A/cm2, respectively. The differential on-resistance (Diff. Ron) of 67.7 mΩ.cm2 and 55.7 mΩ.cm2 are measured at 50 A/cm2 and 100 A/cm2, respectively.

Place, publisher, year, edition, pages
Trans Tech Publications Ltd, 2017
Keywords
Conductivity modulation, Differential on-resistance, Forward voltage drop, Implantation-free, PiN diode, Ultra-high-voltage
National Category
Materials Engineering
Identifiers
urn:nbn:se:kth:diva-216561 (URN)10.4028/www.scientific.net/MSF.897.423 (DOI)2-s2.0-85019990289 (Scopus ID)9783035710434 (ISBN)
Conference
25 September 2016 through 29 September 2016
Note

QC 20171108

Available from: 2017-11-08 Created: 2017-11-08 Last updated: 2017-11-08Bibliographically approved
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Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0001-8108-2631

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