4H-SiC pMOSFETs with Al-doped S/D and NbNi silicide ohmic contacts were demonstrated and were characterized at up to a temperature of 200°C. For the pMOSFETs, silicides on p-type 4H-SiC with Nb/Ni stack, Nb-Ni Alloy, Ni and Nb/Ti were investigated, and the Nb/Ni stack silicide with the contact resistance of 5.04×10-3 Ωcm2 were applied for the pMOSFETs.

This letter reports on a fully integrated 2-linear voltage regulator operational in a wide temperature range from 25 °C up to 500 °C fabricated in 4H-SiC technology. The circuit provides a stable output voltage with less than 1% variation in the entire temperature range. This letter demonstrates the first power supply solution providing both high-temperature (up to 500 °C) and high-load driving capabilities (up to 2).

This letter reports on a fully integrated 2-A linear voltage regulator operational in a wide temperature range from 25 degrees C up to 500 degrees C fabricated in 4H-SiC technology. The circuit provides a stable output voltage with less than 1% variation in the entire temperature range. This letter demonstrates the first power supply solution providing both high-temperature (up to 500 degrees C) and high-load driving capabilities (up to 2 A).

Ring oscillators (ROs) are used to study the high-temperature characteristics of an in-house silicon carbide (SiC) technology. Design and successful operation of the in-house-fabricated 4H-SiC n-p-n bipolar transistors and TTL inverter-based 11-stage RO are reported from 25 degrees C to 600 degrees C. Non-monotonous temperature dependence was observed for the oscillator frequency; in the range of 25 degrees C to 300 degrees C, it increased with the temperature (1.33 MHz at 300 degrees C and V-CC = 15 V), while it decreased in the range of 300 degrees C-600 degrees C. The oscillator output frequency and delay were also characterized over a wide range of supply voltage (10 to 20 V). The noise margins of the TTL inverter were also measured; noise margin low (NML) decreases with the temperature, whereas noise margin high (NMH) increases with the temperature. The measured power-delay product (P-D . T-P) of the TTL inverter and 11-stage RO was approximate to 4.5 and approximate to 285 nJ, respectively, at V-CC= 15 V. Reliability testing indicated that the RO frequency of oscillation decreased 16% after HT characterization.

Implantation-free mesa etched ultra-high-voltage 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. The diode’s design allows a high breakdown voltage of about 19.3 kV according to simulations. No reverse breakdown is observed up to 13 kV with a very low leakage current of 0.1 μA. A forward voltage drop (VF) and differential on-resistance (Diff. Ron) of 9.1 V and 41.4 mΩ cm2 are measured at 100 A/cm2, respectively, indicating the effect of conductivity modulation.

This work presents the design and electrical characterization of in-house-fabricated 2-input NAND gate. The monolithic bipolar 2-input NAND gate employing transistor-transistor logic (TTL) is demonstrated in 4H-SiC and operates over a wide range of temperature and supply voltage. The fabricated circuit was characterized on the wafer by using a hot-chuck probe-station from 25 °C up to 500 °C. The circuit is also characterized over a wide range of voltage supply i.e. 11 to 20 V. The output-noise margin high (NMH) and output-noise margin low (NML) are also measured over a wide range of temperatures and supply voltages using voltage transfer characteristics (VTC). The transient response was measured by applying two square waves of, 5 kHz and 10 kHz. It is demonstrated that the dynamic parameters of the circuit are temperature dependent. The 2-input TTL NAND gate consumes 20 mW at 500 °C and 15 V.

Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10-4 Ω cm2) to epitaxially grown p-type (>5×1018 cm-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni2Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.

Low-parasitic-capacitance 4H-SiC nMOSFETs using a novel self-aligned process were suggested and demonstrated. In these nMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain, drain-source capacitance) were investigated and low parasitic capacitance was achieved by the self-aligned structure

4H-SiC p-i-n photodiodes with various mesa areas (40,000μm2, 2500μm2, 1600μm2, and 400μm2) have been fabricated. Both C-V and I-V characteristics of the photodiodes have been measured at room temperature, 200 °C, 400 °C, and 500 °C. The capacitance and photo current (at 365 nm) of the photodiodes are directly proportional to the area. However, the dark current density increases as the device is scaled down due to the perimeter surface recombination effect. The photo to dark current ratio at the full depletion voltage of the intrinsic layer (-2.7 V) of the photodiode at 500 °C decreases 7 times as the size of the photodiode scales down 100 times. The static and dynamic behavior of the photodiodes are modeled with SPICE parameters at the four temperatures.

Implantation-free mesa etched 10+ kV 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. An area-optimized junction termination extension (O-JTE) is implemented in order to achieve a high breakdown voltage. The diodes design allows a high breakdown voltage of about 19.3 kV according to simulations by Sentaurus TCAD. No breakdown voltage is recorded up to 10 kV with a very low leakage current of 0.1 μA. The current spreading within the thick drift layer is considered and a voltage drop (VF) of 8.3 V and 11.4 V are measured at 50 A/cm2 and 100 A/cm2, respectively. The differential on-resistance (Diff. Ron) of 67.7 mΩ.cm2 and 55.7 mΩ.cm2 are measured at 50 A/cm2 and 100 A/cm2, respectively.