In this study, we investigate the impact of Gamma Radiation on 4H Silicon Carbide (SiC) Transistor-Transistor Logic (TTL) integrated circuits (ICs), particularly focusing on inverters processed with distinct types of interface oxides: Thermally Grown, Chemical Vapor Deposition, and Atomic Layer Deposition. This research was conducted using a60Co source at Hiroshima University, applying varied radiation doses (17.9 rad(Si)/s, 7.3 rad(Si)/s, and 2.47 rad(Si)/s) to assess the resilience of the SiC inverters under these conditions. Our findings reveal that thermal oxides (Batch 1: W1 and W2) demonstrate higher radiation resilience compared to ALD and CVD interface oxides (Batch 2: W3 and W4), attributable to their denser structure and fewer defects. The study also identifies that while the inverters exhibit marginal degradation at gamma doses nearing 700 krad (under 6%), the most critical operational state is the passive mode (VCC = VIN = 0 V), where the build-up of induced charge in the oxide and interface may lead to early IC degradation of the noise margins. The outcomes from this research provide insights into the processing flow and enhancement of SiC electronics. Our results underscore the potential of SiC-based ICs in environments with high radiation levels, such as space missions, nuclear reactors, and medical applications, due to their enhanced radiation tolerance.

There is extensive use of nondestructive test (NDT) inspections on aircraft, and many techniques nowadays exist to inspect failures and cracks in their structures. Moreover, NDT inspections are part of a more general structural health monitoring (SHM) system, where cutting-edge technologies are needed as powerful resources to achieve high performance. The high-performance aspects of SHM systems are response time, power consumption, and usability, which are difficult to achieve because of the system's complexity. Then, it is even more challenging to develop a real-time low-power SHM system. Today, the ideal process is for structural health information extraction to be completed on the flight; however, the defects and damage are quantitatively made offline and on the ground, and sometimes, the respective procedure test is applied later on the ground, after the flight. For this reason, the present paper introduces an FPGA-based intelligent SHM system that processes Lamb wave signals using piezoelectric sensors to detect, classify, and locate damage in composite structures. The system employs machine learning (ML), specifically support vector machines (SVM), to classify damage while addressing outlier challenges with the Mahalanobis distance during the classification phase. To process the complex Lamb wave signals, the system incorporates well-known signal processing (DSP) techniques, including power spectrum density (PSD), wavelet transform, and Principal Component Analysis (PCA), for noise reduction, feature extraction, and data compression. These techniques enable the system to handle material anisotropy and mitigate the effects of edge reflections and mode conversions. Damage is quantitatively evaluated with classification accuracies of 96.25% for internal defects and 97.5% for external defects, with localization achieved by associating receiver positions with damage occurrence. This robust system is validated through experiments and demonstrates its potential for real-time applications in aerospace composite structures, addressing challenges related to material complexity, outliers, and scalable hardware implementation for larger sensor networks.

In this study, we introduce the impact of gamma irradiation on 4H-SiC based transistor-transistor logic (TTL) inverters. These monolithic bipolar inverters have been successfully demonstrated in a broad spectrum of temperature and supply voltage conditions. In this iteration of experiments, attempts made to the processing to increase beta values. The gamma radiation tests from a60 Co source were conducted under various operation conditions and measured in-situ under different biasing conditions. The Silicon Carbide Integrated circuits ( SiC ICs) show excellent tolerance properties to gamma radiation up to doses of nearly 1 MRad. Comparable Si BJT-based TTL inverters show considerable degradation already at one order of magnitude lower doses, clearly demonstrating the superior radiation hardness of 4H-SiC ICs.

Gamma irradiation effects have been investigated on 4H-silicon carbide (SiC) bipolar junction transistors (BJTs), where the devices were exposed under different biasing regimes such as saturation, cut-off, active, reverse, and zero bias. Since bipolar transistors can be affected by dose rate, three different dose rates were used during irradiation tests. Characterization was performed on the transistors, without irradiation but in situ to avoid delays between irradiation and characterization. The study explores the relationship between biasing conditions and their impact on radiation-induced degradation of SiC BJT transistors. From these experiments, it is clear that 4H-SiC bipolar transistors can withstand high gamma doses, in the worst case less than 22% degradation of the current gain was seen for doses of up to 2 Mrad(Si).

The self-aligned silicide (salicide) process, where a metallic silicide is formed without lithographic definition to both source/drain-regions and the gate, is important for devices thanks to its ability to minimize parasitic resistances in scaled silicon CMOS technology. The challenge to transfer the process to SiC technology is two-fold: a single silicide has to give low resistance contacts to both ion implanted p-type and n-type simultaneously, and the typical temperatures required to form contacts to SiC is high enough that silicide agglomerates on polysilicon. In this work, we investigated if there exists a process window for salicide process for the purpose of developing a salicide process for SiC CMOS. Transfer length method structures were fabricated by ion implantation of phosphorus and aluminum to investigate simultaneous contacts to SiC. Bridge resistor structures (2μm width) were fabricated both with and without silicide-block to determine the silicide stability on highly in-situ doped polysilicon. The approach is design of experiment with multiple factors, including silicide composition, annealing temperature, deposited metal thickness and annealing time. The formation of self-aligned low resistive contacts to both n-type and p-type SiC was successful. The mutual process window for the co-existence of stable silicide on polysilicon and low resistive contacts to SiC, which is required for true salicide process, could not be found.

An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part has 256 ( $16\times 16$ ) pixels. The digital circuit part for row and column selection contains two 4-to-16 decoders and one 8-bit counter. The digital circuits are designed in transistor-transistor logic (TTL). The entire circuit has 1959 transistors. It is the first demonstration of SiC opto-electronic on-chip integration. The function of the image sensor up to 400 degrees C has been verified by taking photos of the spatial patterns masked from UV light. The image sensor would play a significant role in UV photography, which has important applications in astronomy, clinics, combustion detection and art.

Silicon carbide (SiC) is a wide band gap material that is slowly but steadily asserting itself as a reliable alternative to silicon (Si) for high temperature electronics applications, in particular for the electrical vehicles industry. The passivation of SiC devices with diamond films is expected to decrease leakage currents and avoid premature breakdown of the devices, leading to more efficient devices. However, for an efficient passivation the interface between both materials needs to be virtually void free and high quality diamond films are required from the first stages of growth. In order to evaluate the impact of the deposition and seeding parameters in the properties of the deposits, diamond films were deposited on SiC substrates by hot filament chemical vapor deposition (HFCVD). Before the seeding step the substrates were exposed to diamond growth conditions (pretreatment PT) and seeding was performed with a solution of detonation nanodiamond (DND) particles and with 6-12 and 40-60 mu m grit. Diamond films were then grown at different temperatures and with different methane concentrations and the deposits were observed in a scanning electron microscope (SEM); their quality was assessed with Raman spectroscopy.

Control of defects at or near the MOS interface is paramount for device performance optimization. The SiC MOS system is known to exhibit two types of MOS defects,defects at the SiO₂/SiC interface and defects inside of the gate oxide that can trap channel charge carriers. Differentiating these two types can be challenging. In this work, we use several electrical measurement techniques to extract and separate these two types of defects. The charge pumping method and the ultrafast pulsed I-V method are given focus, as they are independent methods for extracting the defects inside the gate oxide. Defects are extracted from low voltage n-channel MOSFETs with differently processed gate oxides: steam-treatment, dry oxidation and nitridation. Ultrafast pulsed I-V and charge pumping gives comparable results. The presented analysis of the electrical characterization methods is of use for SiC MOSFET process development.

Low-parasitic-capacitance 4H-SiC pMOSFETs were demonstrated for high-frequency CMOS inverters. In these pMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain capacitance) were investigated and low parasitic capacitance was achieved by the trench gate structure.