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BETA
Zetterling, Carl-MikaelORCID iD iconorcid.org/0000-0001-8108-2631
Alternative names
Publications (10 of 209) Show all publications
Hou, S., Shakir, M., Hellström, P.-E., Malm, B. G., Zetterling, C.-M. & Östling, M. (2020). A Silicon Carbide 256 Pixel UV Image Sensor Array Operating at 400 degrees C. IEEE Journal of the Electron Devices Society, 8(1), 116-121
Open this publication in new window or tab >>A Silicon Carbide 256 Pixel UV Image Sensor Array Operating at 400 degrees C
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2020 (English)In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 8, no 1, p. 116-121Article in journal (Refereed) Published
Abstract [en]

An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part has 256 ( $16\times 16$ ) pixels. The digital circuit part for row and column selection contains two 4-to-16 decoders and one 8-bit counter. The digital circuits are designed in transistor-transistor logic (TTL). The entire circuit has 1959 transistors. It is the first demonstration of SiC opto-electronic on-chip integration. The function of the image sensor up to 400 degrees C has been verified by taking photos of the spatial patterns masked from UV light. The image sensor would play a significant role in UV photography, which has important applications in astronomy, clinics, combustion detection and art.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2020
Keywords
Silicon carbide (SiC), image sensor, ultraviolet (UV), photodiode, high temperature, bipolar junction transistor (BJT), transistor-transistor logic (TTL)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-270881 (URN)10.1109/JEDS.2020.2966680 (DOI)000515658000001 ()2-s2.0-85079349461 (Scopus ID)
Note

QC 20200325

Available from: 2020-03-25 Created: 2020-03-25 Last updated: 2020-03-25Bibliographically approved
Mukherjee, D., Oliveira, F., Trippe, S. C., Rotter, S., Neto, M., Silva, R., . . . Mendes, J. C. (2020). Deposition of diamond films on single crystalline silicon carbide substrates. Diamond and related materials, 101, Article ID 107625.
Open this publication in new window or tab >>Deposition of diamond films on single crystalline silicon carbide substrates
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2020 (English)In: Diamond and related materials, ISSN 0925-9635, E-ISSN 1879-0062, Vol. 101, article id 107625Article in journal (Refereed) Published
Abstract [en]

Silicon carbide (SiC) is a wide band gap material that is slowly but steadily asserting itself as a reliable alternative to silicon (Si) for high temperature electronics applications, in particular for the electrical vehicles industry. The passivation of SiC devices with diamond films is expected to decrease leakage currents and avoid premature breakdown of the devices, leading to more efficient devices. However, for an efficient passivation the interface between both materials needs to be virtually void free and high quality diamond films are required from the first stages of growth. In order to evaluate the impact of the deposition and seeding parameters in the properties of the deposits, diamond films were deposited on SiC substrates by hot filament chemical vapor deposition (HFCVD). Before the seeding step the substrates were exposed to diamond growth conditions (pretreatment PT) and seeding was performed with a solution of detonation nanodiamond (DND) particles and with 6-12 and 40-60 mu m grit. Diamond films were then grown at different temperatures and with different methane concentrations and the deposits were observed in a scanning electron microscope (SEM); their quality was assessed with Raman spectroscopy.

Place, publisher, year, edition, pages
Elsevier, 2020
Keywords
DND seeding, CVD diamond, Device passivation, SiC
National Category
Physical Sciences
Identifiers
urn:nbn:se:kth:diva-268808 (URN)10.1016/j.diamond.2019.107625 (DOI)000510954000026 ()2-s2.0-85075194247 (Scopus ID)
Note

QC 20200224

Available from: 2020-02-24 Created: 2020-02-24 Last updated: 2020-02-24Bibliographically approved
Inoue, J., Kuroki, S.-I. -., Ishikawa, S., Maeda, T., Sezaki, H., Makino, T., . . . Zetterling, C.-M. (2019). 4H-SIC trench pMOSFETs for high-frequency CMOS inverters. In: Silicon Carbide and Related Materials 2018: . Paper presented at 12th European Conference on Silicon Carbide and Related Materials, ECSCRM 2018, 2-6 September 2018, Birmingham, United Kingdom (pp. 837-840). Trans Tech Publications Ltd
Open this publication in new window or tab >>4H-SIC trench pMOSFETs for high-frequency CMOS inverters
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2019 (English)In: Silicon Carbide and Related Materials 2018, Trans Tech Publications Ltd , 2019, p. 837-840Conference paper, Published paper (Refereed)
Abstract [en]

Low-parasitic-capacitance 4H-SiC pMOSFETs were demonstrated for high-frequency CMOS inverters. In these pMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain capacitance) were investigated and low parasitic capacitance was achieved by the trench gate structure.

Place, publisher, year, edition, pages
Trans Tech Publications Ltd, 2019
Series
Materials Science Forum, ISSN 1662-9752 ; 963
Keywords
4H-SiC, Harsh environment electronics, Overlapping capacitance, PMOSFET, Capacitance, CMOS integrated circuits, MOSFET devices, Device characteristics, Gate-drain capacitance, Harsh environment, High frequency HF, Parasitic capacitance, Trench gate structures, Silicon carbide
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-262430 (URN)10.4028/www.scientific.net/MSF.963.837 (DOI)2-s2.0-85071890235 (Scopus ID)9783035713329 (ISBN)
Conference
12th European Conference on Silicon Carbide and Related Materials, ECSCRM 2018, 2-6 September 2018, Birmingham, United Kingdom
Note

QC 20191104

Available from: 2019-11-04 Created: 2019-11-04 Last updated: 2019-11-04Bibliographically approved
Kargarrazi, S., Elahipanah, H., Saggini, S., Senesky, D. & Zetterling, C.-M. (2019). 500 degrees C SiC PWM Integrated Circuit. IEEE transactions on power electronics, 34(3), 1997-2001
Open this publication in new window or tab >>500 degrees C SiC PWM Integrated Circuit
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2019 (English)In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 34, no 3, p. 1997-2001Article in journal (Refereed) Published
Abstract [en]

This letter reports on a high-temperature pulsewidth modulation (PWM) integrated circuit microfabricated in 4H-SiC bipolar process technology that features an on-chip integrated ramp generator. The circuit has been characterized and shown to be operational in a wide temperature range from 25 to 500 degrees C. The operating frequency of the PWM varies in the range of 160 to 210 kHz and the duty cycle varies less than 17% over the entire temperature range. The proposed PWM is suggested to efficiently and reliably control power converters in extreme environments.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2019
Keywords
Bipolar junction transistor (BJT), high-temperature integrated circuit (IC), pulsewidth modulator (PWM), silicon carbide
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-244489 (URN)10.1109/TPEL.2018.2859430 (DOI)000458179200003 ()2-s2.0-85050612857 (Scopus ID)
Note

QC 20190321

Available from: 2019-03-21 Created: 2019-03-21 Last updated: 2019-03-21Bibliographically approved
Shakir, M., Hou, S., Metreveli, A., Rashid, A. U., Mantooth, H. A. & Zetterling, C.-M. (2019). 555-Timer and Comparators Operational at 500 degrees C. IEEE Transactions on Electron Devices, 66(9), 3734-3739
Open this publication in new window or tab >>555-Timer and Comparators Operational at 500 degrees C
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2019 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, no 9, p. 3734-3739Article in journal (Refereed) Published
Abstract [en]

This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 degrees C-500 degrees C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2019
Keywords
Bipolar SiC 555-timer integrated circuit (IC), high temperature ( HT) ICs, SiC ICs, transistor-transistor logic (TTL) comparator
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-259423 (URN)10.1109/TED.2019.2925915 (DOI)000482583200005 ()2-s2.0-85071318661 (Scopus ID)
Note

QC 20190924

Available from: 2019-09-24 Created: 2019-09-24 Last updated: 2019-09-24Bibliographically approved
Shakir, M. (2019). 555-Timer IC Operational at 500 °C. Bipolar SiC 555-timer IC, High Temperature ICs, TTL Comparator, SiC Integrated Circuits
Open this publication in new window or tab >>555-Timer IC Operational at 500 °C
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2019 (English)In: Bipolar SiC 555-timer IC, High Temperature ICs, TTL Comparator, SiC Integrated CircuitsArticle in journal (Other academic) [Artistic work] Submitted
Abstract [en]

This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. The paper demonstrates the 555-timer ICs characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 to 500°C. Nonmonotonictemperature dependence was observed for the 555-timer IC frequency, rise-time, fall-time, and power dissipation.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-251765 (URN)
Funder
Knut and Alice Wallenberg Foundation
Note

QC 20190523

Available from: 2019-05-21 Created: 2019-05-21 Last updated: 2019-05-23Bibliographically approved
Hou, S., Hellström, P.-E., Zetterling, C.-M. & Östling, M. (2019). A 4H-SiC BJT as a Switch for On-Chip Integrated UV Photodiode. IEEE Electron Device Letters, 40(1), 51-54
Open this publication in new window or tab >>A 4H-SiC BJT as a Switch for On-Chip Integrated UV Photodiode
2019 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 40, no 1, p. 51-54Article in journal (Refereed) Published
Abstract [en]

This letter presents the design, fabrication, and characterization of a 4H-SiC n-p-n bipolar junction transistor as a switch controlling an on-chip integrated p-i-n photodiode. The transistor and photodiode share the same epitaxial layers and topside contacts for each terminal. By connecting the collector of the transistor and the anode of the photodiode, the photo current from the photodiode is switched off at low base voltage (cutoff region of the transistor) and switched on at high base voltage (saturation region of the transistor). The transfer voltage of the circuit decreases as the ambient temperature increases (2 mV/degrees C). Both the on-state and off-state current of the circuit have a positive temperature coefficient and the on/off ratio is >80 at temperature ranged from 25 degrees C to 400 degrees C. It is proposed that the on/off ratio can be increased by similar to 1000 times by adding a light blocking layer on the transistor to reduce light induced off-state current in the circuit.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2019
Keywords
4H-SiC, BJT, UV, photodiode, high temperature, switch
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-242990 (URN)10.1109/LED.2018.2883749 (DOI)000456172600013 ()2-s2.0-85057777289 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation
Note

QC 20190204

Available from: 2019-02-04 Created: 2019-02-04 Last updated: 2019-04-10Bibliographically approved
Shakir, M., Hou, S. & Zetterling, C.-M. (2019). A Monolithic 500 °C D-flip flop Realized in Bipolar 4H-SiC TTL technology. In: : . Paper presented at Materials Science Forum, Proceedings of European Conference on Silicon Carbide and Related Materials 2018.
Open this publication in new window or tab >>A Monolithic 500 °C D-flip flop Realized in Bipolar 4H-SiC TTL technology
2019 (English)Conference paper, Poster (with or without abstract) (Other academic) [Artistic work]
Keywords
TTL-based DFF, Bipolar SiC integrated circuits, High-temperature integrated circuits (ICs), Transistor-transistor logic (TTL), Bipolar junction transistor (BJT), Digital gates
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-251764 (URN)
Conference
Materials Science Forum, Proceedings of European Conference on Silicon Carbide and Related Materials 2018
Note

QC 20190523

Available from: 2019-05-21 Created: 2019-05-21 Last updated: 2019-05-23Bibliographically approved
Ekström, M., Malm, B. G. & Zetterling, C.-M. (2019). High-Temperature Recessed Channel SiC CMOS Inverters and Ring Oscillators. IEEE Electron Device Letters, 40(5), 670-673
Open this publication in new window or tab >>High-Temperature Recessed Channel SiC CMOS Inverters and Ring Oscillators
2019 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 40, no 5, p. 670-673Article in journal (Refereed) Published
Abstract [en]

Digital electronics in SiC find use in high-temperature applications. The objective of this study was to fabricate SiC CMOS without using ion implantation. In this letter, we present a recessed channel CMOS process. Selective doping is achieved by etching epitaxial layers into mesas. A deposited SiO2-film, post-annealed at lowtemperature and re-oxidized in pyrogenic steam, is used as the gate oxide to produce a conformal gate oxide over the non-planar topography. PMOS, NMOS, inverters, and ring oscillators are characterized at 200 °C. The PMOS requires reduced threshold voltage in order to enable long term reliability. This result demonstrates that it is possible to fabricate SiC CMOS without ion implantation and by low-temperature processing.

Keywords
Inverter, recessed channel, ring oscillator (RO), silicon carbide (4H-SiC), static CMOS
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-250275 (URN)10.1109/LED.2019.2903184 (DOI)000466190700002 ()2-s2.0-85064992240 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation, Working on VenusSwedish Foundation for Strategic Research , CMP Lab
Note

QC 20190428

Available from: 2019-04-27 Created: 2019-04-27 Last updated: 2019-10-24Bibliographically approved
Ekström, M., Ferrario, A. & Zetterling, C.-M. (2019). Investigation of a Self-Aligned Cobalt Silicide Process for Ohmic Contacts to Silicon Carbide. Journal of Electronic Materials, 48(4), 2509-2516
Open this publication in new window or tab >>Investigation of a Self-Aligned Cobalt Silicide Process for Ohmic Contacts to Silicon Carbide
2019 (English)In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 48, no 4, p. 2509-2516Article in journal (Refereed) Published
Abstract [en]

Previous studies showed that cobalt silicide can form ohmic contacts to p-type 6H-SiC by directly reacting cobalt with 6H-SiC. Similar results can be achieved on 4H-SiC, given the similarities between the different silicon carbide polytypes. However, previous studies using multilayer deposition of silicon/cobalt on 4H-SiC gave ohmic contacts to n-type. In this study, we investigated the cobalt silicide/4H-SiC system to answer two research questions. Can cobalt contacts be self-aligned to contact holes to 4H-SiC? Are the self-aligned contacts ohmic to n-type, p-type, both or neither? Using x-ray diffraction, it was found that a mixture of silicides (Co2Si and CoSi) was reliably formed at 800°C using rapid thermal processing. The cobalt silicide mixture becomes ohmic to epitaxially grown n-type (1×1019cm-3) if annealed at 1000°C, while it shows rectifying properties to epitaxially grown p-type (1×1019cm-3) for all tested anneal temperatures in the range 800–1000°C. The specific contact resistivity (ρC) to n-type was 4.3×10-4 Ω cm2. This work opens the possibility to investigate other self-aligned contacts to silicon carbide.

Place, publisher, year, edition, pages
Springer, 2019
Keywords
Cobalt (Co), rapid thermal processing (RTP), self-aligned silicide, silicon carbide (4H-SiC), transfer length method (TLM)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-250274 (URN)10.1007/s11664-019-07020-0 (DOI)000460453100095 ()2-s2.0-85061514454 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation, Working on Venus
Note

QC 20190428

Available from: 2019-04-27 Created: 2019-04-27 Last updated: 2019-04-29Bibliographically approved
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ORCID iD: ORCID iD iconorcid.org/0000-0001-8108-2631

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