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Publications (10 of 109) Show all publications
Ivanisevic, N., Rodriguez, S. & Rusu, A. (2018). A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 05
Open this publication in new window or tab >>A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems
2018 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 05Article in journal (Refereed) Accepted
Abstract [en]

This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-229446 (URN)10.1109/TCSI.2018.2838135 (DOI)
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-06-04 Created: 2018-06-04 Last updated: 2018-06-04Bibliographically approved
Hussain, M. W., Elahipanah, H., Zumbro, J. E., Schröder, S., Rodriguez, S., Malm, B. G., . . . Rusu, A. (2018). A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology. IEEE Electron Device Letters, 39(6), 855-858
Open this publication in new window or tab >>A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology
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2018 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 6, p. 855-858Article in journal (Refereed) Accepted
Abstract [en]

This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.

Place, publisher, year, edition, pages
IEEE Press, 2018
Keywords
4H-SiC BJTs, high-temperature, RF, mixer
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-228486 (URN)10.1109/LED.2018.2829628 (DOI)000437086800018 ()2-s2.0-85045754083 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation
Note

QC 20180601

Available from: 2018-05-25 Created: 2018-05-25 Last updated: 2018-07-23Bibliographically approved
Hussain, M. W., Elahipanah, H., Schröder, S., Rodriguez, S., Malm, B. G., Östling, M. & Rusu, A. (2018). An Intermediate Frequency Amplifier for High-Temperature Applications. IEEE Transactions on Electron Devices, 65(4), 1411-1418
Open this publication in new window or tab >>An Intermediate Frequency Amplifier for High-Temperature Applications
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2018 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 65, no 4, p. 1411-1418Article in journal (Refereed) Accepted
Abstract [en]

This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than-7 and-11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base-collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
4H-silicon carbide (4H-SiC) bipolar junction transistors (BJTs), high temperature, intermediate frequency (IF) amplifiers, matching networks
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-227642 (URN)10.1109/TED.2018.2804392 (DOI)000427856300022 ()2-s2.0-85042860667 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation
Note

QC 20180509

Available from: 2018-05-09 Created: 2018-05-09 Last updated: 2018-06-01Bibliographically approved
Ivanisevic, N., Rodriguez, S. & Rusu, A. (2018). Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation. In: : . Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS) 2018. Florence, Italy: IEEE
Open this publication in new window or tab >>Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation
2018 (English)Conference paper, Published paper (Refereed)
Abstract [en]

A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is −133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

Place, publisher, year, edition, pages
Florence, Italy: IEEE, 2018
Series
IEEE International Symposium on Circuits and Systems (ISCAS), E-ISSN 2379-447X
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-229449 (URN)10.1109/ISCAS.2018.8351377 (DOI)978-1-5386-4881-0 (ISBN)978-1-5386-4882-7 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS) 2018
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-06-04 Created: 2018-06-04 Last updated: 2018-06-04Bibliographically approved
Katic, J., Rodriguez, S. & Rusu, A. (2017). A High-Efficiency Energy Harvesting Interface for Implanted Biofuel Cell and Thermal Harvesters. IEEE transactions on power electronics, 33(5), 4125-4134, Article ID 7940053.
Open this publication in new window or tab >>A High-Efficiency Energy Harvesting Interface for Implanted Biofuel Cell and Thermal Harvesters
2017 (English)In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 33, no 5, p. 4125-4134, article id 7940053Article in journal (Refereed) Published
Abstract [en]

A dual-source energy harvesting interface that combines energy from implanted glucose biofuel cell and thermoelectric generator is presented. A single-inductor dual-input dual-output boost converter topology is employed to efficiently transfer the extracted power to the output. A dual-input feature enables the simultaneous maximum power extraction from two harvesters, while a dual-output allows a control circuit to perform complex digital functions at nW power levels. The control circuit reconfigures the converter to improve the efficiency and achieve zero-current and zero-voltage switching. The measurement results of the proposed boost converter, implemented in a 0.18 μm CMOS process, show a peak efficiency of 89.5% when both sources provide a combined input power of 66 μW. In the single-source mode, the converter achieves a peak efficiency of 85.2% at 23 μW for the thermoelectric source and 90.4% at 29 μW for the glucose biofuel cell. The converter can operate from minimum input voltages of 10 mV for the thermoelectric source and 30 mV for the glucose biofuel cell. 

Place, publisher, year, edition, pages
IEEE Press, 2017
Keywords
Energy harvesting, DC-DC power conversion, CMOS integrated circuits, thermoelectric energy conversion, fuel cells
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-206586 (URN)10.1109/TPEL.2017.2712668 (DOI)000424832200039 ()2-s2.0-85041930625 (Scopus ID)
Projects
Mi-SoC
Funder
Swedish Research Council
Note

QC 20170508

Available from: 2017-05-05 Created: 2017-05-05 Last updated: 2018-05-24Bibliographically approved
Ivanisevic, N., Rodriguez, S. & Rusu, A. (2017). Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach. In: 2017 IEEE Biomedical Circuits and Systems Conference, Turin, October 19-21, 2017: . Paper presented at 2017 IEEE Biomedical Circuits and Systems Conference. Turin, Italy
Open this publication in new window or tab >>Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach
2017 (English)In: 2017 IEEE Biomedical Circuits and Systems Conference, Turin, October 19-21, 2017, Turin, Italy, 2017Conference paper, Poster (with or without abstract) (Refereed)
Abstract [en]

Impedance spectroscopy is a low-cost sensing technique that is generating considerable interest in wearable and implantable biomedical applications since it can be efficiently integrated on a single microchip. In this paper, the fundamental characteristics of the most well-known system architectures are presented, and a more robust and hardware-efficient solution is proposed. An all-digital implementation based on adaptive filtering is used for identifying the impedance parameters of a sample-under-test. The coefficients of an infinite-impulse-response (IIR) filter are tuned by an adaptive algorithm based on pseudo-linear regression and output-error formulation. A three-level pseudorandom noise generator with a concave power spectral density is employed without deteriorating the nominal performance. Proof-of-concept has been verified with behavioral simulations.

Place, publisher, year, edition, pages
Turin, Italy: , 2017
Keywords
Adaptive algorithms, Clocks, Frequency measurement, Impedance, Impedance measurement, Spectroscopy, Systems architecture
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-225867 (URN)10.1109/BIOCAS.2017.8325148 (DOI)978-1-5090-5803-7 (ISBN)
Conference
2017 IEEE Biomedical Circuits and Systems Conference
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-04-10 Created: 2018-04-10 Last updated: 2018-06-04Bibliographically approved
Ivanisevic, N., Rodriguez, S. & Rusu, A. (2016). A 96.4 dB High-Pass Delta-Sigma Modulator with Dynamic Biasing and Tree-Structured DEM. In: 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS): . Paper presented at 14th IEEE International New Circuits and Systems Conference (NEWCAS), JUN 26-29, 2016, Vancouver, CANADA. Vancouver, Canada: IEEE, Article ID 7604762.
Open this publication in new window or tab >>A 96.4 dB High-Pass Delta-Sigma Modulator with Dynamic Biasing and Tree-Structured DEM
2016 (English)In: 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), Vancouver, Canada: IEEE, 2016, article id 7604762Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a switched-capacitor high-pass delta-sigma modulator that can directly convert a chopper modulated signal to the digital domain. Low power consumption is achieved by employing inverter-based amplifiers and dynamic biasing in the first amplifier with relaxed slew-rate requirements as a result of the multi-bit quantization. The mismatch errors in the switched-capacitor DAC are first-order noise shaped by a tree-structured dynamic element matching encoder. Schematic level simulations show that the high-pass modulator achieves a peak SNDR of 96.4 dB and a SFDR of 101 dBc over a bandwidth of 300 Hz. The total estimated power consumption of the modulator is 19.56 mu W leading to a figure-of-merit of 0.6 pJ/conv.

Place, publisher, year, edition, pages
Vancouver, Canada: IEEE, 2016
Series
IEEE International New Circuits and Systems Conference
Keywords
delta-sigma, ADC, modulator, switched-capacitor, DEM, dynamic, element, matching
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-198993 (URN)10.1109/NEWCAS.2016.7604762 (DOI)000386900400028 ()2-s2.0-84999014708 (Scopus ID)978-1-4673-8900-6 (ISBN)
Conference
14th IEEE International New Circuits and Systems Conference (NEWCAS), JUN 26-29, 2016, Vancouver, CANADA
Funder
Swedish Research Council
Note

QC 20170116

Available from: 2017-01-16 Created: 2016-12-22 Last updated: 2017-01-25Bibliographically approved
Tao, S. & Rusu, A. (2016). A Comparative Design Study of Continuous-Time Incremental Sigma-Delta ADC Architectures. International journal of circuit theory and applications, 44(12), 2147-2163
Open this publication in new window or tab >>A Comparative Design Study of Continuous-Time Incremental Sigma-Delta ADC Architectures
2016 (English)In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 44, no 12, p. 2147-2163Article in journal (Refereed) Published
Abstract [en]

This paper presents a comparative design study of continuous-time (CT) incremental sigma-delta (IΣΔ) ADCs, which can expand another dimension of the IΣΔ ADC world that is dominated by discrete-time implementations. Several CT IΣΔ ADC architectures are introduced and analyzed aiming to reduce the modulator’s sampling frequency and consequently the power dissipation. Based on the analytical results, three CT IΣΔ ADCs are selected to be examined, implemented, and tested. The three ADC prototypes, fabricated in a standard 0.18 μm CMOS technology, demonstrate competitive figure-of-merits in terms of power efficiency compared to the state-of-the-art counterparts.

Place, publisher, year, edition, pages
John Wiley & Sons, 2016
Keywords
A/D conversion; incremental sigma-delta; continuous-time; extended-range; two-step
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-185162 (URN)000389841700008 ()2-s2.0-84971012114 (Scopus ID)
Funder
Swedish Research Council
Note

QC 20160512

Available from: 2016-04-11 Created: 2016-04-11 Last updated: 2017-11-30Bibliographically approved
Katic, J., Rodriguez, S. & Rusu, A. (2016). A Dual-Output Thermoelectric Energy Harvesting Interface with 86.6% Peak Efficiency at 30 μW and Total Control Power of 160 nW. IEEE Journal of Solid-State Circuits
Open this publication in new window or tab >>A Dual-Output Thermoelectric Energy Harvesting Interface with 86.6% Peak Efficiency at 30 μW and Total Control Power of 160 nW
2016 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173XArticle in journal (Refereed) Published
Abstract [en]

A thermoelectric energy harvesting interface based on a single-inductor dual-output (SIDO) boost converter is presented. A system-level design methodology combined with ultra-low power circuit techniques reduce the power consumption and minimize the losses within the converter. Additionally, accurate zero-current switching (ZCS) and zero-voltage switching (ZVS) techniques are employed in the control circuit to ensure high conversion efficiency at μW input power levels. The proposed SIDO boost converter is implemented in a 0.18 μm CMOS process and can operate from input voltages as low as 15 mV. The measurement results show that the converter achieves a peak conversion efficiency of 86.6% at 30 μW input power.

Place, publisher, year, edition, pages
IEEE Solid-State Circuits Society, 2016
Keywords
Boost converter, energy harvesting, single-inductor dual-output, zero-current switching, zero-voltage switching, dead time, low-power design
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-186514 (URN)10.1109/JSSC.2016.2561959 (DOI)2-s2.0-84986321427 (Scopus ID)
Projects
Mi-SoC
Funder
Swedish Research Council
Note

QC 20160517

Available from: 2016-05-12 Created: 2016-05-12 Last updated: 2017-11-30Bibliographically approved
Rodriguez, S., Tao, S. & Rusu, A. (2016). Advances in Technologies for Implantable Bioelectronics. In: Pietro Salvo and Miguel Hernandez-Silveira (Ed.), Wireless Medical Systems and Algorithms: Design and Applications (pp. 3-20). CRC Press
Open this publication in new window or tab >>Advances in Technologies for Implantable Bioelectronics
2016 (English)In: Wireless Medical Systems and Algorithms: Design and Applications / [ed] Pietro Salvo and Miguel Hernandez-Silveira, CRC Press, 2016, p. 3-20Chapter in book (Refereed)
Place, publisher, year, edition, pages
CRC Press, 2016
Keywords
implantable electronics adc
National Category
Embedded Systems Medical Equipment Engineering
Research subject
Medical Technology
Identifiers
urn:nbn:se:kth:diva-184237 (URN)978-1-4987-0076-4 (ISBN)978-1-4987-0078-8 (ISBN)
Projects
VR ErBioVR Mi-SoC
Funder
Swedish Research Council
Note

QC 20160418

Available from: 2016-03-31 Created: 2016-03-31 Last updated: 2016-04-18Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0003-3802-7834

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