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Attarzadeh Niaki, Seyed HoseinORCID iD iconorcid.org/0000-0002-2171-1528
Alternative names
Publications (10 of 19) Show all publications
Attarzadeh-Niaki, S.-H., Altinel, E., Koedam, M., Molnos, A., Sander, I. & Goossens, K. (2015). A Composable and Predictable MPSoC Design Flow for Multiple Real-Time Applications. In: : . Paper presented at 1st Workshop on Model-Implementation Fidelity (MiFi), March 13, 2015, Grenoble,France.
Open this publication in new window or tab >>A Composable and Predictable MPSoC Design Flow for Multiple Real-Time Applications
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2015 (English)Conference paper, Oral presentation only (Refereed)
Abstract [en]

Design of real-time MPSoC systems including multiple appli-cations is challenging because temporal requirements of each applicationmust be respected throughout the entire design flow. Currently the de-sign of different applications is often interdependent, making converge toa solution for each application difficult. This paper proposes a composi-tional method to design applications independently, and then to executethem without interference. We define a formal modeling framework as asuitable entry point for application design. The models are executable,which enables early detection of specification errors, and include the for-mal properties of the applications based on well-defined models of com-putation. We combine this with a predictable MPSoC platform templatethat has a supporting design flow but lacks a simulation front-end. Thestructure and behavior of the application models are exported to an in-termediate format via introspection which is iteratively adapted for thebackend flow. We identify the problems arising in this adaptation andprovide appropriate solutions. The design flow is demonstrated by a sys-tem consisting of two streaming applications where less than half of thedesign time is dedicated to operating on the integrated system model.

Keywords
System-level design languages, Automated design flow, Real- time applications, Composable system, Time-predictable architectures
National Category
Embedded Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:kth:diva-160912 (URN)
Conference
1st Workshop on Model-Implementation Fidelity (MiFi), March 13, 2015, Grenoble,France
Note

QC 20150319

Available from: 2015-03-03 Created: 2015-03-03 Last updated: 2015-03-19Bibliographically approved
Diallo, P. I., Attarzadeh-Niaki, S. H., Robino, F., Sander, I., Champeau, J. & Öberg, J. (2015). A formal, model-driven design flow for system simulation and multi-core implementation. In: 2015 10th IEEE International Symposium on Industrial Embedded Systems: . Paper presented at 10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015; Siegen; Germany (pp. 254-263). IEEE
Open this publication in new window or tab >>A formal, model-driven design flow for system simulation and multi-core implementation
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2015 (English)In: 2015 10th IEEE International Symposium on Industrial Embedded Systems, IEEE , 2015, p. 254-263Conference paper, Published paper (Refereed)
Abstract [en]

With the growing complexity of Real-Time Embedded Systems (RTES), there is a huge interest in using modeling languages such as the Unified Modeling Language (UML), and other Model-Driven Engineering (MDE) techniques targeting RTES system design. These approaches provide language abstractions for system design, allowing to focus on their relevant properties. Unfortunately, such approaches still suffer from several shortcomings including the lack of well-defined semantics. Therefore, it remains difficult to connect the MDE specification tools and the design tools that are based on formal grounds and well-defined semantics to perform analysis, validation or system synthesis for RTES. This paper presents a top-down RTES design flow aiming to reduce the gap between MDE and formal design approaches. We present the connection between a framework dedicated to the enrichment of modeling languages such as UML with formal semantics, a framework based on formal models of computation supporting validation by simulation, and a system synthesis tool targeting a flexible platform with well-defined execution services. Our purpose is to cover several system design phases from specification, simulation down to implementation on a platform. As a case study, a JPEG Encoder application was realized following the different design steps of the tool-chain.

Place, publisher, year, edition, pages
IEEE, 2015
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-187135 (URN)10.1109/SIES.2015.7185067 (DOI)000380569800033 ()2-s2.0-84959543996 (Scopus ID)978-1-4673-7711-9 (ISBN)
External cooperation:
Conference
10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015; Siegen; Germany
Note

QC 20160518

Available from: 2016-05-18 Created: 2016-05-17 Last updated: 2016-09-06Bibliographically approved
Attarzadeh Niaki, S. H., Mikulcak, M. & Sander, I. (2015). Automatic Generation of Virtual Prototypes from Platform Templates. In: Marie-Minerve Louërat, Torsten Maehne (Ed.), Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2013 (pp. 147-166). Switzerland: Springer
Open this publication in new window or tab >>Automatic Generation of Virtual Prototypes from Platform Templates
2015 (English)In: Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2013 / [ed] Marie-Minerve Louërat, Torsten Maehne, Switzerland: Springer, 2015, p. 147-166Chapter in book (Refereed)
Abstract [en]

Virtual Prototypes (VPs) provide an early development platform to embedded software designers when the hardware is not ready yet and allows them to explore the design space of a system, both from the software and architecture perspective. However, automatic generation of VPs is not straightforward because several aspects such as the validity of the generated platforms and the timing of the components needs to be considered. To address this problem, based on a framework which characterizes predictable platform templates, we propose a method for automated generation of VPs which is integrated into a combined design flow consisting of analytic and simulation based design-space exploration. Using our approach the valid TLM-2.0-based simulated VP instances with timing annotation can be generated automatically and used for further development of the system in the design flow. We have demonstrated the potential of our method by designing a JPEG encoder system.

Place, publisher, year, edition, pages
Switzerland: Springer, 2015
Series
Lecture Notes in Electrical Engineering, ISSN 1876-1100 ; 311
Keywords
Design automation, Design Space Exploration (DSE), Predictable platforms, Real-time systems, Simulation Virtual Prototype (VP), Mixed-Criticality System (MCS), Transaction-Level Modeling (TLM), Constraint programming, Analytical models, Interoperability
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-155935 (URN)10.1007/978-3-319-06317-1_8 (DOI)2-s2.0-84906871426 (Scopus ID)978-3-319-06316-4 (ISBN)978-3-319-06317-1 (ISBN)
Note

QC 20141117

Available from: 2014-11-15 Created: 2014-11-15 Last updated: 2014-11-17Bibliographically approved
Attarzadeh Niaki, S. H., Mikulcak, M., Robino, F. & Sander, I. (2014). A Framework for Characterizing Predictable Platform Templates. Stockholm, Sweden: KTH Royal Institute of Technology
Open this publication in new window or tab >>A Framework for Characterizing Predictable Platform Templates
2014 (English)Report (Other academic)
Abstract [en]

The design of real-time multiprocessor systems is a very costly and time-consuming process due to the need for extensive verification efforts. Genericcorrect-by-construction system-level design flows, targeting predictable plat-forms, would help to tackle this problem. Unfortunately, because system-level design problems are formulated monolithically, existing methods areeither not powerful enough to perform efficient design space exploration,over-customized to a specific class of platforms, or do not allow to be ex-tended with new heuristics and solving methods, which makes their reusedifficult. We present a formal framework to explicitly capture and character-ize predictable platform templates that can be used to formulate a genericdesign flow for real-time streaming applications in a composable manner. Aproof-of-concept implementation of such a flow is performed and used to mapa JPEG encoder application onto an FPGA-based time-predictable platform.

Place, publisher, year, edition, pages
Stockholm, Sweden: KTH Royal Institute of Technology, 2014. p. 18
Series
TRITA-ICT/ECS R, ISSN 1653-7238 ; 14:01
Keywords
automation, design-space exploration, predictable platforms, real-time systems
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-148162 (URN)KTH/ICT/ECS/R-14-01-SE (ISRN)
Note

QC 20140819

Available from: 2014-08-01 Created: 2014-08-01 Last updated: 2014-11-17Bibliographically approved
Attarzadeh Niaki, S. H. (2014). Managing the Complexity in Embedded and Cyber-Physical System Design: System Modeling and Design-Space Exploration. (Doctoral dissertation). Stockholm: KTH Royal Institute of Technology
Open this publication in new window or tab >>Managing the Complexity in Embedded and Cyber-Physical System Design: System Modeling and Design-Space Exploration
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

To cope with the increasing complexity of embedded and cyber-physical system design, different system-level design approaches are proposed which start from abstract models and implement them using design flows with high degrees of automation. However, creating models of such systems and also formulating the mathematical problems arising in these design flows are themselves challenging tasks. A promising approach is the composable construction of these models and problems from more basic entities. Unfortunately, it is non-trivial to propose such compositional formulations today because the current practice in the electronic design automation domain tends to be on using imperative languages and frameworks due to legacy and performance-oriented reasons.

This thesis addresses the system design complexity by first promoting proper formalisms and frameworks for capturing models and formulating design-space exploration problems for electronic system-level design in a declarative style; and second, propose realizations based on the industrially accepted languages and frameworks which hold the interesting properties such as composability and parallelism.

For modeling, ForSyDe, a denotational system-level modeling formalism for heterogeneous embedded systems is chosen, extended with timed domains to make it more appropriate for capturing cyber-physical systems, and mapped on top of the IEEE standard system design language SystemC. The realized modeling framework, called ForSyDe-SystemC, can be used for modeling systems of heterogeneous nature and their composition to form more sophisticated systems and also conducting parallel and distributed simulation for boosting the simulation speed. Another extension to ForSyDe, named wrapper processes, introduces the ability to compose formal ForSyDe models with legacy IP blocks running in external execution environments to perform a heterogeneous co-simulation.

In platform-based design flows, the correct and optimal mapping of an application model onto a flexible platform involves solving a hard problem, named design space exploration. This work proposes Tahmuras, a constraint- based framework to construct generic design space exploration problems as the composition of three individual sub-problems: the application, the platform, and the mapping and scheduling problems. In this way, the model of the design space exploration problem in Tahmuras is automatically generated for each combination of application semantics, target platform, and mapping and scheduling policy simply by composing their respective problems. Using constraint programming, problems can be modeled in a declarative style, while they can be solved in a variety of different styles, including imperative solving heuristics commonly used to solve difficult problems. Efficient parallel solvers exists for constraint programming. 

Abstract [sv]

Den ökande komplexiteten är en stor utmaning för konstruktionen av framtida inbyggda system. För att möta utmaningen utvecklas nu konstruktionsmetoder som har som mål att starta från en abstrakt modell och att generera en implementering genom ett konstruktionsflöde med hög automatiseringsgrad. Dessvärre är dock skapandet av abstrakta systemmodeller och formaliseringen av de relaterade matematiska problemen i sig ett mycket utmanande problem. Konstruktion genom komposition av basenheter är en lovande idé, men tyvärr är det väldigt svårt att introducera metoden i dagens industriella konstruktionsflöden på grund av imperativa programmeringsspråk och ett gammalt arv i form av existerande kodbas och äldre konstruktioner.

Avhandlingen adresserar komplexiten inom systemkonstruktion genom att föreslå passande formalismer för att uttrycka modeller i en deklarativ stil och angripa problemet att hitta en passande implementering. Dessutom visar avhandlingen hur dessa formalismer kan realiseras i en form som kan användas i ett industriellt sammanhang utan att förlora formalismens viktiga grundläggande egenskaper som komposition och parallelism.

Modelleringen använder och utökar ForSyDe, en konstruktionsmetod för heterogena inbyggda system. Tilläggen består av en modelleringsmodell som kan fånga specifika egenskaper hos heterogena inbyggda system, samt en implementering av ForSyDe i SystemC, ett industriellt modelleringsspråk som är standardiserat av IEEE. Den nya utvecklingsmiljön, ForSyDe-SystemC, kan användas för att modellera inbyggda system, komponera systemmodeller till större system, samt möjliggör genomförandet av parallella och distribuerade simuleringar med medföljande hög simuleringshastighet. Avhandlingen introducerar också “wrapper”-konceptet i ForSyDe som möjliggör integrationen av existerande modeller och system som en del av en formell ForSyDe-modell och deras co-simulering. ForSyDe-SystemC har använts inom EU-projekt av industriella partner för modellering av egna system.

Att hitta en korrekt och effektiv implementering av en abstrakt systemmodell är målet inom aktiviteten “design space exploration” (DSE) som är ett svårt problem för parametriserbara och flexibla plattformar. Avhandlingen presenterar två generationer av Tahmuras, som är baserade på villkorsprogrammering och har som mål att konstruera DSE-problemet som en komposition av tre olika delproblem: applikation, plattform, och bindning. Ett integrerat DSE-problem kan sedan automatiskt genereras genom en kombination av dessa delproblem. Olika metoder, från heuristisk till komplett sökning, kan användas inom villkorsprogrammering för att lösa DSE-problemet. För att visa Tahmuras potential har DSE-metoden validerats med hjälp av olika systemapplikationer av skilda tidsegenskaper och olika plattformar. 

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2014. p. xvi, 104
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 14:12
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-155939 (URN)978-91-7595-286-4 (ISBN)
Public defence
2014-12-05, Sal B, Electrum 229, KTH-ICT, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20141117

Available from: 2014-11-17 Created: 2014-11-15 Last updated: 2014-11-17Bibliographically approved
Attarzadeh Niaki, S. H. & Sander, I. (2013). An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013: . Paper presented at Design, Automation & Test in Europe (DATE'13); Grenoble, France, 18-22 March 2013 (pp. 27-30).
Open this publication in new window or tab >>An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems
2013 (English)In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, p. 27-30Conference paper, Published paper (Refereed)
Abstract [en]

Simulation of complex embedded and cyber-physical systems requires exploitation of the computation power ofavailable parallel architectures. Current simulation environments either do not address this parallelism or use separate models for parallel simulation and for analysis and synthesis, which might lead to model mismatches. We extend a formal modeling framework targeting heterogeneous systems with elements that enable parallel simulations. An automated flow is then proposed that starting from a serial executable specification generates an efficient MPI-based parallel simulation model by using aconstraint-based method. The proposed flow generates parallel models with acceptable speedups for a representative example.

Series
Design, Automation, and Test in Europe Conference and Exhibition. Proceedings, ISSN 1530-1591
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-121772 (URN)10.7873/DATE.2013.020 (DOI)2-s2.0-84885575736 (Scopus ID)978-1-4673-5071-6 (ISBN)
Conference
Design, Automation & Test in Europe (DATE'13); Grenoble, France, 18-22 March 2013
Note

QC 20130822

Available from: 2013-05-03 Created: 2013-05-03 Last updated: 2014-11-17Bibliographically approved
Attarzadeh Niaki, S. H., Mikulcak, M. & Sander, I. (2013). Rapid virtual prototyping of real-time systems using predictable platform characterizations. In: Forum on Specification Design Languages (FDL) 2013: . Paper presented at 2013 16th Forum on Specification and Design Languages, FDL 2013; Paris; France; 24 September 2013 through 26 September 2013 (pp. 6646652).
Open this publication in new window or tab >>Rapid virtual prototyping of real-time systems using predictable platform characterizations
2013 (English)In: Forum on Specification Design Languages (FDL) 2013, 2013, p. 6646652-Conference paper, Published paper (Refereed)
Abstract [en]

Virtual prototypes (VPs) provide an early development platform to embedded software designers when the hardware is not ready yet and allows them to explore the design space of a system, both from the software and architecture perspective. However, automatic generation of VPs is not straightforward because several aspects such as the validity of the generated platforms and the timing of the components needs to be considered. To address this problem, based on a framework which characterizes predictable platform templates, we propose a method for automated generation of VPs which is integrated into a combined design flow consisting of analytic and simulation based design-space exploration. Using our approach the valid TLM 2.0-based simulated VP instances with timing annotation can be generated automatically and used for further development of the system in the design flow. We have demonstrated the potential of our method by designing a JPEG encoder system.

Series
Forum on Specification and Design Languages, ISSN 1636-9874
Keywords
automation, design-space exploration, predictable platforms, real-time systems, simulation, virtual prototyping
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-136365 (URN)2-s2.0-84891332661 (Scopus ID)978-295305048-6 (ISBN)
Conference
2013 16th Forum on Specification and Design Languages, FDL 2013; Paris; France; 24 September 2013 through 26 September 2013
Note

QC 20140205

Available from: 2013-12-04 Created: 2013-12-04 Last updated: 2014-02-05Bibliographically approved
Herrera, F., Attarzadeh, H. & Sander, I. (2013). Towards a Modelling and Design Framework for Mixed-Criticality SoCs and Systems-of-Systems. In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013: . Paper presented at 16th Euromicro Conference on Digital System Design, DSD 2013; Santander; Spain; 4 September 2013 through 6 September 2013 (pp. 989-996). IEEE conference proceedings
Open this publication in new window or tab >>Towards a Modelling and Design Framework for Mixed-Criticality SoCs and Systems-of-Systems
2013 (English)In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, IEEE conference proceedings, 2013, p. 989-996Conference paper, Published paper (Refereed)
Abstract [en]

Mixed-criticality system (MCS) design is an emerging discipline, which has been identified as a core foundational concept in fields such as cyber-physical systems. The hard real-time design community has pioneered the contributions to MCS design, extending scheduling theory to consider mixed-criticalities and the impact of on-chip and off-chip communication infrastructures. However, the development of MCS design methodologies capable to provide safe and efficient solutions for complex applications and platforms in an acceptable design time demands a more interdisciplinary approach. This paper is a first step towards such an approach in the development of MCS design methodologies. The paper first identifies main design disciplines to be involved in MCS design, both at SoC and system-of-systems (SoS) scales. Then, the paper proposes a core ontology for modelling a mixed-criticality system at both SoC scale (MCSoC) and SoS scale (MCSoS). Finally, the paper introduces a set of aspects required for MCS design which have been identified as open and challenging attending the overviewed state-of-the-art.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2013
Keywords
Systems-of-Systems, Cyber-Physical Systems, Mixed-Criticality, Embedded Distributed Systems
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
SRA - ICT
Identifiers
urn:nbn:se:kth:diva-136412 (URN)10.1109/DSD.2013.112 (DOI)000337235200134 ()2-s2.0-84890065016 (Scopus ID)978-0-7695-5074-9 (ISBN)
Conference
16th Euromicro Conference on Digital System Design, DSD 2013; Santander; Spain; 4 September 2013 through 6 September 2013
Note

QC 20131219

Available from: 2013-12-05 Created: 2013-12-05 Last updated: 2014-09-02Bibliographically approved
Attarzadeh Niaki, S. H., Jakobsen, M. K., Sulonen, T. & Sander, I. (2012). Formal heterogeneous system modeling with SystemC. In: Proceedings of Forum on Specification and Design Languages (FDL) 2012. Paper presented at Forum on Specification and Design Languages (FDL) 2012 (pp. 160-167).
Open this publication in new window or tab >>Formal heterogeneous system modeling with SystemC
2012 (English)In: Proceedings of Forum on Specification and Design Languages (FDL) 2012, 2012, p. 160-167Conference paper, Published paper (Refereed)
Abstract [en]

Electronic System Level (ESL) design of embedded systems proposes raising the abstraction level of the design entry to cope with the increasing complexity of such systems. To exploit the benefits of ESL, design languages should allow specification of models which are a) heterogeneous, to describe different aspects of systems; b) formally defined, for application of analysis and synthesis methods; c) executable, to enable early detection of specification; and d) parallel, to exploit the multi- and many-core platforms for simulation and implementation. We present a modeling library on top of SystemC, targeting heterogeneous embedded system design, based on four models of computation. The library has a formal basis where all elements are well defined and lead in construction of analyzable models. The semantics of communication and computation are implemented by the library, which allows the designer to focus on specifying the pure functional aspects. A key advantage is that the formalism is used to export the structure and behavior of the models via introspection as an abstract representation for further analysis and synthesis.

Keywords
Modeling, Simulation, System-level design, Computer aided engineering, Formal specifications
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-104557 (URN)2-s2.0-84871051725 (Scopus ID)978-1-4673-1240-0 (ISBN)
Conference
Forum on Specification and Design Languages (FDL) 2012
Projects
SYSMODEL
Note

QC 20130122

Available from: 2013-01-11 Created: 2012-11-05 Last updated: 2014-11-17Bibliographically approved
Attarzadeh Niaki, S. H., Beserra, G. S., Andersen, N., Verdon, M. & Sander, I. (2012). Heterogeneous system-level modeling for small and medium enterprises. In: Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on. Paper presented at 2012 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012; Brasilia; 30 August 2012 through 2 September 2012 (pp. 1-6). IEEE conference proceedings
Open this publication in new window or tab >>Heterogeneous system-level modeling for small and medium enterprises
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2012 (English)In: Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on, IEEE conference proceedings, 2012, p. 1-6Conference paper, Published paper (Refereed)
Abstract [en]

The design of today's electronic embedded systems is an increasingly complicated task. This is especially problematic for Small and Medium Enterprises (SMEs) which have limited resources. In this work, we identify a set of common design practices used in industry, with a special focus on problems faced by smaller companies, and formulate them as design scenarios. We show how SMEs can benefit from a system-level design approach by customizing a formal heterogeneous system modeling framework for each scenario. The applicability of this approach is demonstrated by two industrial use cases, an impulse-radio radar and a UART-based protocol.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2012
Keywords
Design practice, Heterogeneous systems, Impulse radios, Industrial use, Small and medium enterprise, System level design, System-level modeling
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-111428 (URN)10.1109/SBCCI.2012.6344450 (DOI)2-s2.0-84870840507 (Scopus ID)978-1-4673-2606-3 (ISBN)
Conference
2012 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012; Brasilia; 30 August 2012 through 2 September 2012
Note

QC 20130121

Available from: 2013-01-11 Created: 2013-01-11 Last updated: 2014-11-17Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-2171-1528

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