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Dentoni da Litta, EugnenioORCID iD iconorcid.org/0000-0003-0333-376X
Alternative names
Publications (10 of 26) Show all publications
Mitrovic, I. Z., Hall, S., Althobaiti, M., Hesp, D., Dhanak, V. R., Santoni, A., . . . Schamm-Chardon, S. (2015). Atomic-layer deposited thulium oxide as a passivation layer on germanium. Journal of Applied Physics, 117(21), Article ID 214104.
Open this publication in new window or tab >>Atomic-layer deposited thulium oxide as a passivation layer on germanium
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2015 (English)In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 117, no 21, article id 214104Article in journal (Refereed) Published
Abstract [en]

A comprehensive study of atomic-layer deposited thulium oxide (Tm2O3) on germanium has been conducted using x-ray photoelectron spectroscopy (XPS), vacuum ultra-violet variable angle spectroscopic ellipsometry, high-resolution transmission electron microscopy (HRTEM), and electron energy-loss spectroscopy. The valence band offset is found to be 3.05±0.2eV for Tm2O3/p-Ge from the Tm 4d centroid and Ge 3p3/2 charge-corrected XPS core-level spectra taken at different sputtering times of a single bulk thulium oxide sample. A negligible downward band bending of ∼0.12eV is observed during progressive differential charging of Tm 4d peaks. The optical band gap is estimated from the absorption edge and found to be 5.77eV with an apparent Urbach tail signifying band gap tailing at ∼5.3eV. The latter has been correlated to HRTEM and electron diffraction results corroborating the polycrystalline nature of the Tm2O3 films. The Tm2O3/Ge interface is found to be rather atomically abrupt with sub-nanometer thickness. In addition, the band line-up of reference GeO2/n-Ge stacks obtained by thermal oxidation has been discussed and derived. The observed low reactivity of thulium oxide on germanium as well as the high effective barriers for holes (∼3eV) and electrons (∼2eV) identify Tm2O3 as a strong contender for interfacial layer engineering in future generations of scaled high-κ gate stacks on Ge.

Keywords
Atomic layer deposition, Electron energy levels, Electron energy loss spectroscopy, Electron scattering, Electrons, Energy dissipation, Energy gap, Germanium, High resolution transmission electron microscopy, Spectroscopic ellipsometry
National Category
Other Physics Topics
Identifiers
urn:nbn:se:kth:diva-170305 (URN)10.1063/1.4922121 (DOI)000355925600026 ()2-s2.0-84930965535 (Scopus ID)
Note

QC 20150629

Available from: 2015-06-29 Created: 2015-06-29 Last updated: 2017-12-04Bibliographically approved
Vaziri, S., Belete, M., Dentoni Litta, E., Smith, A. D., Lupina, G., Lemme, M. C. & Östling, M. (2015). Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors. Nanoscale, 7(30), 13096-13104
Open this publication in new window or tab >>Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors
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2015 (English)In: Nanoscale, ISSN 2040-3364, E-ISSN 2040-3372, Vol. 7, no 30, p. 13096-13104Article in journal (Refereed) Published
Abstract [en]

Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in the literature for applications in electronics and optoelectronics. In this work, the carrier transport mechanisms in semiconductor-insulator-graphene (SIG) capacitors are investigated with respect to their suitability as electron emitters in vertical graphene base transistors (GBTs). Several dielectric materials as tunnel barriers are compared, including dielectric double layers. Using bilayer dielectrics, we experimentally demonstrate significant improvements in the electron injection current by promoting Fowler-Nordheim tunneling (FNT) and step tunneling (ST) while suppressing defect mediated carrier transport. High injected tunneling current densities approaching 103 A cm(-2) (limited by series resistance), and excellent current-voltage nonlinearity and asymmetry are achieved using a 1 nm thick high quality dielectric, thulium silicate (TmSiO), as the first insulator layer, and titanium dioxide (TiO2) as a high electron affinity second layer insulator. We also confirm the feasibility and effectiveness of our approach in a full GBT structure which shows dramatic improvement in the collector on-state current density with respect to the previously reported GBTs. The device design and the fabrication scheme have been selected with future CMOS process compatibility in mind. This work proposes a bilayer tunnel barrier approach as a promising candidate to be used in high performance vertical graphene-based tunneling devices.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-172640 (URN)10.1039/c5nr03002a (DOI)000358615200036 ()26176739 (PubMedID)2-s2.0-84937928928 (Scopus ID)
Funder
Swedish Research CouncilEU, European Research Council, 307311
Note

QC 20150827

Available from: 2015-08-27 Created: 2015-08-27 Last updated: 2017-12-04Bibliographically approved
Garidis, K., Jayakumar, G., Asadollahi, A., Dentoni Litta, E., Hellström, P.-E. & Östling, M. (2015). Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration. In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon: . Paper presented at 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015; Bologna; Italy; 26 January 2015 through 28 January 2015 (pp. 165-168).
Open this publication in new window or tab >>Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration
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2015 (English)In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015, p. 165-168Conference paper, Published paper (Refereed)
Abstract [en]

We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C-350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.

Keywords
3D integration, atomic layer deposition, current leakage, defects, Ge, GeOI, inter layer dielectrics, monolithic, strained Ge, wafer bonding, Deposition, Germanium, Integration, Leakage (fluid), Monolithic integrated circuits, Silicon wafers, Surface roughness, Three dimensional integrated circuits, 3-D integration, Inter-layer dielectrics, Strained-Ge
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-167390 (URN)10.1109/ULIS.2015.7063799 (DOI)000380427400042 ()2-s2.0-84926444085 (Scopus ID)9781479969111 (ISBN)
External cooperation:
Conference
2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015; Bologna; Italy; 26 January 2015 through 28 January 2015
Note

QC 20150529

Available from: 2015-05-29 Created: 2015-05-22 Last updated: 2016-09-02Bibliographically approved
Zoller, C. J., Dentoni Litta, E. & Primetzhofet, D. (2015). Characterization of high-k dielectrics using MeV elastic scattering of He ions. Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, 347, 52-57
Open this publication in new window or tab >>Characterization of high-k dielectrics using MeV elastic scattering of He ions
2015 (English)In: Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, ISSN 0168-583X, E-ISSN 1872-9584, Vol. 347, p. 52-57Article in journal (Refereed) Published
Abstract [en]

We present a systematic comparison of two distinct ion-beam based methods for composition analysis of nanometer oxide films: ion-beam channeling and elastic scattering using nuclear resonances, both at MeV energies. Thin films of the technologically highly relevant high-k dielectrics HfO2 and HfAIO are characterized in the present study, with the additional aim of obtaining a better quantification of the Al content for the latter system. We show that both employed ion scattering methods enable a quantitative determination of the oxygen concentrations with typical uncertainties of about 5-10% in the oxygen fraction. The influence of various kinds of systematic inaccuracies in the evaluation procedure are discussed.

Keywords
RBS, Channeling, EBS, Thin films, High-k dielectrics
National Category
Physical Sciences
Identifiers
urn:nbn:se:kth:diva-163970 (URN)10.1016/j.nimb.2014.12.080 (DOI)000350840200008 ()2-s2.0-84922749076 (Scopus ID)
Note

QC 20150507

Available from: 2015-05-07 Created: 2015-04-13 Last updated: 2017-12-04Bibliographically approved
Dentoni Litta, E., Hellström, P.-E. & Östling, M. (2015). Enhanced channel mobility at sub-nm EOT by integration of a TmSiO interfacial layer in HfO2/TiN high-k/metal gate MOSFETs. IEEE Journal of the Electron Devices Society, 3(5), 397-404, Article ID 7120903.
Open this publication in new window or tab >>Enhanced channel mobility at sub-nm EOT by integration of a TmSiO interfacial layer in HfO2/TiN high-k/metal gate MOSFETs
2015 (English)In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 3, no 5, p. 397-404, article id 7120903Article in journal (Refereed) Published
Abstract [en]

Integration of a high-k interfacial layer (IL) is considered the leading technological solution to extend the scalability of Hf-based high-k/metal gate CMOS technology. We have previously shown that thulium silicate (TmSiO) IL can provide excellent electrical characteristics and enhanced channel mobility at sub-nm EOT. This paper presents a detailed analysis of channel mobility in TmSiO/HfO<inf>2</inf>/TiN MOSFETs, obtained through measurements at varying temperature and under constant voltage stress. We show experimentally for the first time that integration of a high-k IL can benefit mobility by attenuating remote phonon scattering. Specifically, integration of TmSiO results in attenuated remote phonon scattering compared to reference SiO<inf>x</inf>/HfO<inf>2</inf> dielectric stacks having the same EOT, whereas it has no significant influence on remote Coulomb scattering.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2015
Keywords
CMOS, EOT, HfO2, high-k, mobility, RCS, RPS, scattering, silicate, thulium, TmSiO, Carrier mobility, CMOS integrated circuits, Hafnium oxides, Integration, Phonon scattering, Phonons, Silicates, High- k, MOSFET devices
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-175057 (URN)10.1109/JEDS.2015.2443172 (DOI)000369885000002 ()2-s2.0-84940108352 (Scopus ID)
Note

QC 20151207. QC 20160318

Available from: 2015-12-07 Created: 2015-10-09 Last updated: 2016-03-18Bibliographically approved
Litta, E. D., Hellström, P.-E. & Östling, M. (2015). Integration of TmSiO/HfO2 Dielectric Stack in Sub-nm EOT High-k/Metal Gate CMOS Technology. IEEE Transactions on Electron Devices, 62(3), 934-939
Open this publication in new window or tab >>Integration of TmSiO/HfO2 Dielectric Stack in Sub-nm EOT High-k/Metal Gate CMOS Technology
2015 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 934-939Article in journal (Refereed) Published
Abstract [en]

Integration of a high-k interfacial layer (IL) is a promising technological solution to improve the scalability of high-k/metal gate CMOS technology. We have previously demonstrated a CMOS-compatible integration scheme for thulium silicate (TmSiO) IL and shown excellent characteristics in terms of equivalent oxide thickness (EOT), interface state density, channel mobility, and threshold voltage control. Here, we report on optimized annealing conditions leading to gate leakage current density comparable with state-of-the-art SiOx/HfO2 nFETs (0.7 A/cm(2) at 1 V gate bias) at sub-nm EOT (as low as 0.6 nm), with near-symmetric threshold voltages (0.5 V for nFETs and -0.4 V for pFETs). We demonstrate an excellent performance benefit of the TmSiO/HfO2 stack, i.e., improved channel mobility over SiOx/HfO2 dielectric stacks, demonstrating high-field electron and hole mobility of 230 and 70 cm(2)/Vs, respectively, after forming gas anneal at EOT = 0.8 nm. Finally, the reliability of the TmSiO/HfO2/TiN gate stack is investigated, demonstrating 10-year expected life-times for both oxide integrity and threshold voltage stability at an operating voltage of 0.9 V.

Keywords
Bias temperature instability (BTI), CMOS, equivalent oxide thickness (EOT), HfO2, high-k, mobility, reliability, silicate, thulium, thulium silicate (TmSiO), time-dependent dielectric breakdown (TDDB)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-163458 (URN)10.1109/TED.2015.2391179 (DOI)000350332000037 ()2-s2.0-84923644871 (Scopus ID)
Funder
EU, European Research Council, OSIRIS 228229Swedish Foundation for Strategic Research
Note

QC 20150408

Available from: 2015-04-08 Created: 2015-04-07 Last updated: 2017-12-04Bibliographically approved
Olyaei, M., Dentoni Litta, E., Hellström, P.-E., Östling, M. & Malm, B. G. (2015). Low-frequency noise characterization in ultra-low equivalent-oxide-thickness thulium silicate interfacial layer nMOSFETs. IEEE Electron Device Letters, 36(12), 1355-1358
Open this publication in new window or tab >>Low-frequency noise characterization in ultra-low equivalent-oxide-thickness thulium silicate interfacial layer nMOSFETs
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2015 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 12, p. 1355-1358Article in journal (Refereed) Published
Abstract [en]

Low-frequency noise measurements were performed on n-channel MOSFETs with a novel ultra-low 0.3nm EOT interfacial layer (TmSiO) and two different bulk high-k dielectrics (Tm2O3 and HfO2). The MOSFETs were fabricated in a gate-last process and the total gate stack EOT was 1.2 nm and 0.65 nm for the Tm2O3 and HfO2 samples respectively. In general both gate stacks resulted in 1/f type of noise spectra and noise levels comparable to conventional SiO2/HfO2 devices with similar EOTs. The extracted average effective oxide trap density was 2.5×1017 cm-3eV-1 and 1.5×1017 cm-3eV-1 for TmSiO/HfO2 and TmSiO/Tm2O3 respectively. Therefore the best noise performance was observed for the gate stack with Tm2O3 bulk high-k layer and we suggest that the interface free single layer ALD fabrication scheme could explain this.

Place, publisher, year, edition, pages
IEEE Press, 2015
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-177909 (URN)10.1109/LED.2015.2494678 (DOI)000365295300028 ()2-s2.0-84959519144 (Scopus ID)
Funder
EU, European Research Council, OSIRIS/228229
Note

QC 20151130

Available from: 2015-11-30 Created: 2015-11-30 Last updated: 2017-12-01Bibliographically approved
Dentoni Litta, E., Hellström, P.-E. & Östling, M. (2015). Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs. Solid-State Electronics, 108, 24-29
Open this publication in new window or tab >>Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs
2015 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 108, p. 24-29Article in journal (Refereed) Published
Abstract [en]

High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

Keywords
CMOS, Interfacial layer, Threshold voltage, Thulium, TmSiO, Workfunction
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-166313 (URN)10.1016/j.sse.2014.12.008 (DOI)000353004400006 ()2-s2.0-84925632115 (Scopus ID)
Funder
EU, European Research Council, 228229 OSIRIS
Note

QC 20150512

Available from: 2015-05-12 Created: 2015-05-07 Last updated: 2017-12-04Bibliographically approved
Dentoni Litta, E., Hellström, P.-E. & Östling, M. (2014). Effective Workfunction Control in TmSiO/HfO2 high-k/metal gate stacks. In: ULIS 2014: 2014 15th International Conference on Ultimate Integration on Silicon. Paper presented at 15th International Conference on Ultimate Integration on Silicon (ULIS), APR 07-09, 2014, Stockholm, SWEDEN (pp. 69-72).
Open this publication in new window or tab >>Effective Workfunction Control in TmSiO/HfO2 high-k/metal gate stacks
2014 (English)In: ULIS 2014: 2014 15th International Conference on Ultimate Integration on Silicon, 2014, p. 69-72Conference paper, Published paper (Refereed)
Abstract [en]

Integration of high-k interfacial layers in CMOS technology has been proposed to overcome the scaling limitations of the SiOx/HfO2 dielectric stack. Candidate high-k interfacial layers have to be compatible with strict requirements in terms of EOT, inversion layer mobility, threshold voltage control and device reliability. We have previously demonstrated a CMOS-compatible process for integration of thulium silicate (TmSiO) as interfacial layer, providing advantages in terms of EOT and channel mobility. This work demonstrates the compatibility of the TmSiO/HfO2 stack with the threshold voltage control techniques commonly employed in gate-last and gate-first integration schemes, namely the use of a dual-metal process and the integration of dielectric capping layers. We show that the flatband voltage can be set from -1V to +0.5V by proper choice of gate metal, while a shift of 150-400 mV is achievable by means of integration of Al2O3 or La2O3 capping layers.

Series
International Conference on Ultimate Integration on Silicon, ISSN 2330-5738
Keywords
TmSiO, thulium, HfO2, CMOS, interfacial layer, high-k
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-153864 (URN)10.1109/ULIS.2014.6813908 (DOI)000341731300018 ()2-s2.0-84901302996 (Scopus ID)978-1-4799-3718-9 (ISBN)
Conference
15th International Conference on Ultimate Integration on Silicon (ULIS), APR 07-09, 2014, Stockholm, SWEDEN
Note

QC 20141009

Available from: 2014-10-09 Created: 2014-10-09 Last updated: 2016-12-22Bibliographically approved
Dentoni Litta, E., Hellström, P.-E., Henkel, C. & Östling, M. (2014). Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology. Solid-State Electronics, 98, 20-25
Open this publication in new window or tab >>Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology
2014 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 98, p. 20-25Article in journal (Refereed) Published
Abstract [en]

This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500-900 degrees C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1-0.3 nm at low formation temperature and interface state density at flatband condition below 2 x 10(11) cm(-2) eV(-1). The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000 degrees C are also evaluated, achieving an IL EOT of 0.2-0.5 nm, an interface state density at flatband condition similar to 1 x 10(11) cm(-2) eV(-1) and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.

Keywords
TmSiO, LaSiO, Silicate, Interfacial layer, High-k
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-149199 (URN)10.1016/j.sse.2014.04.004 (DOI)000339149000005 ()2-s2.0-84902240457 (Scopus ID)
Funder
EU, European Research Council, 228229 OSIRIS
Note

QC 20140818

Available from: 2014-08-18 Created: 2014-08-18 Last updated: 2017-12-05Bibliographically approved
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ORCID iD: ORCID iD iconorcid.org/0000-0003-0333-376X

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