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Publications (10 of 36) Show all publications
Venica, S., Driussi, F., Vaziri, S., Palestri, P. & Selmi, L. (2017). Graphene Base Transistors With Bilayer Tunnel Barriers: Performance Evaluation and Design Guidelines. IEEE Transactions on Electron Devices, 64(2), 593-598
Open this publication in new window or tab >>Graphene Base Transistors With Bilayer Tunnel Barriers: Performance Evaluation and Design Guidelines
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2017 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, no 2, p. 593-598Article in journal (Refereed) Published
Abstract [en]

Graphene-based capacitors and Graphene base transistors (GBTs) featuring innovative engineered tunnel barriers are characterized in DC and the data are thoroughly analyzed by means of an electrical model and a Monte Carlo transport simulator. Followingmodel calibra-tion on experiments, we then propose strategies to improve the DC common-base current gain and the cutoff frequency of GBTs. The DC and RF performance of optimized GBT structures based on realistic technology data are analyzed in detail to highlight advantages and potential limits of this device concept.

Place, publisher, year, edition, pages
IEEE Press, 2017
Keywords
Analog RF devices, graphene-based devices, modeling
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:kth:diva-204096 (URN)10.1109/TED.2016.2636447 (DOI)000394691600037 ()2-s2.0-85008429711 (Scopus ID)
Note

QC 20170329

Available from: 2017-03-29 Created: 2017-03-29 Last updated: 2018-01-13Bibliographically approved
Illarionov, Y., Waltl, M., Smith, A. D., Vaziri, S., Östling, M., Lemme, M. C. & Grasser, T. (2016). Bias-temperature instability on the back gate of single-layer double-gated graphene field-effect transistors. Paper presented at International Conference on Solid State Devices and Materials (SSDM), SEP 27-30, 2015, Sapporo, JAPAN. Japanese Journal of Applied Physics, 55(4), Article ID 04EP03.
Open this publication in new window or tab >>Bias-temperature instability on the back gate of single-layer double-gated graphene field-effect transistors
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2016 (English)In: Japanese Journal of Applied Physics, ISSN 0021-4922, E-ISSN 1347-4065, Vol. 55, no 4, article id 04EP03Article in journal (Refereed) Published
Abstract [en]

We study the positive and negative bias-temperature instabilities (PBTI and NBTI) on the back gate of single-layer double-gated graphene fieldeffect transistors (GFETs). By analyzing the resulting degradation at different stress times and oxide fields we show that there is a significant asymmetry between PBTI and NBTI with respect to their dependences on these parameters. Finally, we compare the results obtained on the high-k top gate and SiO2 back gate of the same device and show that SiO2 gate is more stable with respect to BTI.

Place, publisher, year, edition, pages
Institute of Physics (IOP), 2016
Keywords
Graphene, Graphene transistors, Integrated circuits, Reconfigurable hardware, Back gates, Bias temperature instability, Graphene field-effect transistors, High- k, Negative bias temperature instability, Single layer, Stress time, Top gate
National Category
Physical Sciences
Identifiers
urn:nbn:se:kth:diva-187205 (URN)10.7567/JJAP.55.04EP03 (DOI)000373929400152 ()2-s2.0-84963650746 (Scopus ID)
Conference
International Conference on Solid State Devices and Materials (SSDM), SEP 27-30, 2015, Sapporo, JAPAN
Funder
EU, European Research Council
Note

QC 20160519

Available from: 2016-05-19 Created: 2016-05-18 Last updated: 2017-11-30Bibliographically approved
Östling, M., Smith, A., Vaziri, S., Delekta, S. S., Li, J. & Lemme, M. C. (2016). Emerging graphene device technologies. In: Emerging Nanomaterials and Devices: . Paper presented at Symposium on Emerging Nanomaterials and Devices - PRiME 2016/230th ECS Meeting, Honolulu, United States, 2 October 2016 through 7 October 2016 (pp. 17-35). Electrochemical Society, 75(13), Article ID 13.
Open this publication in new window or tab >>Emerging graphene device technologies
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2016 (English)In: Emerging Nanomaterials and Devices, Electrochemical Society, 2016, Vol. 75, no 13, p. 17-35, article id 13Conference paper, Published paper (Refereed)
Abstract [en]

Graphene has a wide range of attractive electrical and mechanical properties. This unique blend of properties make it a good candidate for emerging and future device technologies, such as sensors, high frequency electronics, and energy storage devices. In this review paper, each of the aforementioned applications will be explored along with demonstrations of their operating principles. Specifically, we explore pressure and humidity sensors, graphene base transistor for high frequency applications, and supercapacitors. In addition, this paper provides a general overview of these graphene technologies and, in the case of pressure and humidity sensors, benchmarking against other competing technologies. This paper further shows possible and prospective paths that are suitable for future graphene research to take.

Place, publisher, year, edition, pages
Electrochemical Society, 2016
Series
ECS Transactions, ISSN 1938-5862 ; 75
Keywords
Graphene, Graphene transistors, Humidity sensors, Nanostructured materials, Competing technologies, Device technologies, Electrical and mechanical properties, High-frequency applications, High-frequency electronics, Operating principles, Review papers, Super capacitor, Graphene devices
National Category
Materials Engineering
Identifiers
urn:nbn:se:kth:diva-195484 (URN)10.1149/07513.0017ecst (DOI)000406653800003 ()2-s2.0-84991503834 (Scopus ID)9781607685395 (ISBN)
Conference
Symposium on Emerging Nanomaterials and Devices - PRiME 2016/230th ECS Meeting, Honolulu, United States, 2 October 2016 through 7 October 2016
Funder
Swedish Research Council, 2014-6160EU, European Research Council, 641416Stiftelsen Olle Engkvist Byggmästare, 2014/799VINNOVA, 2015-01337
Note

QC 20161125

Available from: 2016-11-25 Created: 2016-11-03 Last updated: 2017-08-25Bibliographically approved
Vaziri, S. (2016). Graphene Hot-electron Transistors. (Doctoral dissertation). Stockholm: KTH Royal Institute of Technology
Open this publication in new window or tab >>Graphene Hot-electron Transistors
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Graphene base transistors (GBTs) have been, recently, proposed to overcome the intrinsic limitations of the graphene field effect transistors (GFETs) and exploit the graphene unique properties in high frequency (HF) applications. These devices utilize single layer graphene as the base material in the vertical hot-electron transistors. In an optimized GBT, the ultimate thinness of the graphene-base and its high conductivity, potentially, enable HF performance up to the THz region.  This thesis presents an experimental investigation on the GBTs as well as integration process developments for the fabrication of graphene-based devices.

In this work, a full device fabrication and graphene integration process were designed with high CMOS compatibility considerations. To this aim, basic process modules, such as graphene transfer, deposition of materials on graphene, and formation of tunnel barriers, were developed and optimized. A PDMS-supporting graphene transfer process were introduced to facilitate the wet/dry wafer-scale transfer from metal substrate onto an arbitrarily substrate. In addition, dielectric deposition on graphene using atomic layer deposition (ALD) was investigated. These dielectric layers, mainly, served as the base-collector insulators in the fabricated GBTs. Moreover, the integration of silicon (Si) on the graphene surface was studied.

Using the developed fabrication process, the first proof of concept devices were demonstrated. These devices utilized 5 nm-thick silicon oxide (SiO2) and about 20 nm-thick aluminum oxide (Al2O3) as the emitter-base insulator (EBI) and base-collector insulator (BCI). The direct current (DC) functionality of these devices exhibited >104 on/off current ratios and a current transfer ratio of about 6%. The performance of these devices was limited by the non-optimized barrier parameters and device manufacturing technology.

The possibility to improve and optimize the GBT performance was demonstrated by applying different barrier optimization approaches. Comparing to the proof of concept devices, several orders of magnitude higher injection current density was achieved using a bilayer dielectric tunnel barrier. Utilizing the novel TmSiO/TiO2 (1 nm/6 nm) dielectric stack, this tunnel barrier prevents defect mediated tunneling and, simultaneously, promotes the Fowler-Nordheim tunneling (FNT) and step tunneling (ST). Furthermore, it was shown that Si/graphene Schottky junction can significantly improve the current gain by reducing the electron backscattering at the base-collector barrier. In this thesis, a maximum current transfer ratio of about 35% has been achieved.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2016. p. xviii, 81
Series
TRITA-ICT ; 2016:08
Keywords
Graphene, hot-electron transistors, graphene base transistors, GBT, cross-plane carrier transport, tunneling, ballistic transport, heterojunction transistors, graphene integration, graphene transfer
National Category
Engineering and Technology
Research subject
Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-186044 (URN)978-91-7595-932-0 (ISBN)
Public defence
2016-05-26, SAL C, Electrum 229, Kista, 10:00 (English)
Opponent
Supervisors
Funder
EU, FP7, Seventh Framework Programme, 317839EU, European Research Council, 228229
Note

QC 20160503

Available from: 2016-05-03 Created: 2016-04-29 Last updated: 2017-05-23Bibliographically approved
Vaziri, S., Belete, M., Dentoni Litta, E., Smith, A. D., Lupina, G., Lemme, M. C. & Östling, M. (2015). Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors. Nanoscale, 7(30), 13096-13104
Open this publication in new window or tab >>Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors
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2015 (English)In: Nanoscale, ISSN 2040-3364, E-ISSN 2040-3372, Vol. 7, no 30, p. 13096-13104Article in journal (Refereed) Published
Abstract [en]

Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in the literature for applications in electronics and optoelectronics. In this work, the carrier transport mechanisms in semiconductor-insulator-graphene (SIG) capacitors are investigated with respect to their suitability as electron emitters in vertical graphene base transistors (GBTs). Several dielectric materials as tunnel barriers are compared, including dielectric double layers. Using bilayer dielectrics, we experimentally demonstrate significant improvements in the electron injection current by promoting Fowler-Nordheim tunneling (FNT) and step tunneling (ST) while suppressing defect mediated carrier transport. High injected tunneling current densities approaching 103 A cm(-2) (limited by series resistance), and excellent current-voltage nonlinearity and asymmetry are achieved using a 1 nm thick high quality dielectric, thulium silicate (TmSiO), as the first insulator layer, and titanium dioxide (TiO2) as a high electron affinity second layer insulator. We also confirm the feasibility and effectiveness of our approach in a full GBT structure which shows dramatic improvement in the collector on-state current density with respect to the previously reported GBTs. The device design and the fabrication scheme have been selected with future CMOS process compatibility in mind. This work proposes a bilayer tunnel barrier approach as a promising candidate to be used in high performance vertical graphene-based tunneling devices.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-172640 (URN)10.1039/c5nr03002a (DOI)000358615200036 ()26176739 (PubMedID)2-s2.0-84937928928 (Scopus ID)
Funder
Swedish Research CouncilEU, European Research Council, 307311
Note

QC 20150827

Available from: 2015-08-27 Created: 2015-08-27 Last updated: 2017-12-04Bibliographically approved
Vaziri, S., Smith, A. D., Östling, M., Lupina, G., Dabrowski, J., Lippert, G., . . . Lemme, M. C. (2015). Going ballistic: Graphene hot electron transistors. Solid State Communications, 224, 64-75
Open this publication in new window or tab >>Going ballistic: Graphene hot electron transistors
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2015 (English)In: Solid State Communications, ISSN 0038-1098, E-ISSN 1879-2766, Vol. 224, p. 64-75Article in journal (Refereed) Published
Abstract [en]

This paper reviews the experimental and theoretical state of the art in ballistic hot electron transistors that utilize two-dimensional base contacts made from graphene, i.e. graphene base transistors (GBTs). Early performance predictions that indicated potential for THz operation still hold true today, even with improved models that take non-idealities into account. Experimental results clearly demonstrate the basic functionality, with on/off current switching over several orders of magnitude, but further developments are required to exploit the full potential of the GBT device family. In particular, interfaces between graphene and semiconductors or dielectrics are far from perfect and thus limit experimental device integrity, reliability and performance.

Place, publisher, year, edition, pages
Elsevier, 2015
Keywords
Graphene, Hot electron transistors graphene base transistor, GBT, HBT, Ballistic transport, NEGF
National Category
Physical Sciences
Identifiers
urn:nbn:se:kth:diva-180239 (URN)10.1016/j.ssc.2015.08.012 (DOI)000366070300013 ()2-s2.0-84947603528 (Scopus ID)
Note

QC 20160118

Available from: 2016-01-18 Created: 2016-01-08 Last updated: 2017-11-30Bibliographically approved
Illarionov, Y., Smith, A., Vaziri, S., Östling, M., Mueller, T., Lemme, M. & Grasser, T. (2015). Hot-Carrier Degradation and Bias-Temperature Instability in Single-Layer Graphene Field-Effect Transistors: Similarities and Differences. IEEE Transactions on Electron Devices, 62(11), 3876-3881
Open this publication in new window or tab >>Hot-Carrier Degradation and Bias-Temperature Instability in Single-Layer Graphene Field-Effect Transistors: Similarities and Differences
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2015 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 11, p. 3876-3881Article in journal (Refereed) Published
Abstract [en]

We present a detailed analysis of hot-carrier degradation (HCD) in graphene field-effect transistors (GFETs) and compare those findings with the bias-temperature instability (BTI). Our results show that the HCD in GFETs is recoverable, similar to its BTI counterpart. Moreover, both the degradation mechanisms strongly interact. Particular attention is paid to the dynamics of HCD recovery, which can be well fitted with the capture/emission time (CET) map model and the universal relaxation function for some stress conditions, quite similar to the BTI in both GFETs and Si technologies. The main result of this paper is an extension of our systematic method for benchmarking new graphene technologies for the case of HCD.

Place, publisher, year, edition, pages
IEEE, 2015
Keywords
Bias-temperature instability (BTI), graphene FETs (GFETs), hot-carrier degradation (HCD), reliability
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-177949 (URN)10.1109/TED.2015.2480704 (DOI)000364242000064 ()2-s2.0-84946142854 (Scopus ID)
Note

QC 20151202

Available from: 2015-12-02 Created: 2015-11-30 Last updated: 2017-12-01Bibliographically approved
Illarionov, Y. u., Waltl, M., Smith, A. D., Vaziri, S., Östling, M., Mueller, T., . . . Grasser, T. (2015). Hot-carrier degradation in single-layer double-gated graphene field-effect transistors. In: IEEE International Reliability Physics Symposium Proceedings: . Paper presented at IEEE International Reliability Physics Symposium, IRPS 2015, 19 April 2015 through 23 April 2015 (pp. XT21-XT26). IEEE conference proceedings
Open this publication in new window or tab >>Hot-carrier degradation in single-layer double-gated graphene field-effect transistors
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2015 (English)In: IEEE International Reliability Physics Symposium Proceedings, IEEE conference proceedings, 2015, p. XT21-XT26Conference paper, Published paper (Refereed)
Abstract [en]

We report a first study of hot-carrier degradation (HCD) in graphene field-effect transistors (GFETs). Our results show that HCD in GFETs is recoverable, similarly to the bias-temperature instability (BTI). Depending on the top gate bias polarity, the presence of HCD may either accelerate or suppress BTI. Contrary to BTI, which mainly results in a change of the charged trap density in the oxide, HCD also leads to a mobility degradation which strongly correlates with the magnitude of the applied stress.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2015
Keywords
Graphene, Hot carriers, Integrated circuits, Applied stress, Bias temperature instability, Charged traps, Graphene field effect transistor (GFETs), Graphene field-effect transistors, Hot carrier degradation, Mobility degradation, Single layer, Field effect transistors
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-181557 (URN)10.1109/IRPS.2015.7112834 (DOI)000371888900167 ()2-s2.0-84942912989 (Scopus ID)9781467373623 (ISBN)
Conference
IEEE International Reliability Physics Symposium, IRPS 2015, 19 April 2015 through 23 April 2015
Note

QC 20160304

Available from: 2016-03-04 Created: 2016-02-02 Last updated: 2016-04-11Bibliographically approved
Illarionov, Y. u., Waltl, M., Smith, A. D., Vaziri, S., Östling, M., Lemme, M. C. & Crasser, T. (2015). Impact of hot carrier stress on the defect density and mobility in double-gated graphene field-effect transistors. In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon: . Paper presented at 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015, 26 January 2015 through 28 January 2015 (pp. 81-84).
Open this publication in new window or tab >>Impact of hot carrier stress on the defect density and mobility in double-gated graphene field-effect transistors
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2015 (English)In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015, p. 81-84Conference paper, Published paper (Refereed)
Abstract [en]

We study the impact of hot-carrier degradation (HCD) on the performance of graphene field-effect transistors (GFETs) for different polarities of HC and bias stress. Our results show that the impact of HCD consists in a change of both charged defect density and carrier mobility. At the same time, the mobility degradation agrees with an attractive/repulsive scattering asymmetry and can be understood based on the analysis of the defect density variation.

Keywords
Carrier mobility, Defect density, Defects, Graphene, Hot carriers, Bias stress, Charged defect density, Density variations, Graphene field effect transistor (GFETs), Graphene field-effect transistors, Hot carrier degradation, Hot carrier stress, Mobility degradation, Field effect transistors
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-168326 (URN)10.1109/ULIS.2015.7063778 (DOI)000380427400021 ()2-s2.0-84926435163 (Scopus ID)9781479969111 (ISBN)
External cooperation:
Conference
2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015, 26 January 2015 through 28 January 2015
Note

QC 20150608

Available from: 2015-06-08 Created: 2015-06-02 Last updated: 2016-09-02Bibliographically approved
Illarionov, Y., Waltl, M., Smith, A., Vaziri, S., Östling, M., Lemme, M. & Grasser, T. (2015). Interplay between hot carrier and bias stress components in single-layer double-gated graphene field-effect transistors. In: European Solid-State Device Research Conference: . Paper presented at 45th European Solid-State Device Research Conference, ESSDERC 2015, 14 September 2015 through 18 September 2015 (pp. 172-175). IEEE
Open this publication in new window or tab >>Interplay between hot carrier and bias stress components in single-layer double-gated graphene field-effect transistors
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2015 (English)In: European Solid-State Device Research Conference, IEEE , 2015, p. 172-175Conference paper, Published paper (Refereed)
Abstract [en]

We examine the interplay between the degradations associated with the bias-temperature instability (BTI) and hot carrier degradation (HCD) in single-layer double-gated graphene field-effect transistors (GFETs). Depending on the polarity of the applied BTI stress, the HCD component acting in conjuction can either accelerate or compensate the degradation. The related phenomena are studied in detail at different temperatures. Our results show that the variations of the charged trap density and carrier mobility induced by both contributions are correlated. Moreover, the electron/hole mobility behaviour agrees with the previously reported attractive/repulsive scattering asymmetry. © 2015 IEEE.

Place, publisher, year, edition, pages
IEEE, 2015
Keywords
Charge carrier processes, Degradation, Graphene, Logic gates, Performance evaluation, Stress, Transistors, Graphene transistors, Hot carriers, Reconfigurable hardware, Solid state devices, Stresses, Bias temperature instability, Charge carrier process, Charged traps, Graphene field effect transistor (GFETs), Graphene field-effect transistors, Hot carrier degradation, Single layer, Field effect transistors
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-186834 (URN)10.1109/ESSDERC.2015.7324741 (DOI)000376615800041 ()2-s2.0-84959349571 (Scopus ID)9781467371339 (ISBN)
Conference
45th European Solid-State Device Research Conference, ESSDERC 2015, 14 September 2015 through 18 September 2015
Note

QC 20160517

Available from: 2016-05-17 Created: 2016-05-13 Last updated: 2016-06-20Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0003-1234-6060

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