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Publications (10 of 14) Show all publications
Wang, X., Bleiker, S. J., Edinger, P., Errando-Herranz, C., Roxhed, N., Stemme, G., . . . Niklaus, F. (2019). Wafer-Level Vacuum Sealing by Transfer Bonding of Silicon Caps for Small Footprint and Ultra-Thin MEMS Packages. Journal of microelectromechanical systems, 28(3), 460-471
Open this publication in new window or tab >>Wafer-Level Vacuum Sealing by Transfer Bonding of Silicon Caps for Small Footprint and Ultra-Thin MEMS Packages
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2019 (English)In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 28, no 3, p. 460-471Article in journal (Refereed) Published
Abstract [en]

Vacuum and hermetic packaging is a critical requirement for optimal performance of many micro-electro-mechanical systems (MEMS), vacuum electronics, and quantum devices. However, existing packaging solutions are either elaborate to implement or rely on bulky caps and footprint-consuming seals. Here, we address this problem by demonstrating a wafer-level vacuum packaging method featuring transfer bonding of 25-μm-thin silicon (Si) caps that are transferred from a 100-mm-diameter silicon-on-insulator (SOI) wafer to a cavity wafer to seal the cavities by gold-aluminum (Au-Al) thermo-compression bonding at a low temperature of 250 °C. The resulting wafer-scale sealing yields after wafer dicing are 98% and 100% with sealing rings as narrow as 6 and 9 μm, respectively. Despite the small sealing footprint, the Si caps with 9-μm-wide sealing rings demonstrate a high mean shear strength of 127 MPa. The vacuum levels in the getter-free sealed cavities are measured by residual gas analysis to be as low as 1.3 mbar, based on which a leak rate smaller than 2.8x10-14 mbarL/s is derived. We also show that the thickness of the Si caps can be reduced to 6 μm by post-transfer etching while still maintaining excellent hermeticity. The demonstrated ultra-thin packages can potentially be placed in between the solder bumps in flip-chip interfaces, thereby avoiding the need of through-cap-vias in conventional MEMS packages.

Keywords
Vacuum, hermetic, packaging, sealing, MEMS, ultra-thin package, small footprint, transfer bonding, 3D integration, flip chip, aluminum, gold, thermo-compression bonding.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-250639 (URN)10.1109/JMEMS.2019.2910985 (DOI)000470838300018 ()
Funder
EU, Horizon 2020, 780283
Note

QC 20190619

Available from: 2019-04-30 Created: 2019-04-30 Last updated: 2020-02-19Bibliographically approved
Bleiker, S. J., Dubois, V. J., Schröder, S., Ottonello Briano, F., Gylfason, K. B., Stemme, G. & Niklaus, F. (2018). Adhesive Wafer Bonding for Heterogeneous System Integration. In: The Electrochemical Society (Ed.), ECS Meeting Abstracts: . Paper presented at Americas International Meeting on Electrochemistry and Solid State Science (AiMES 2018).
Open this publication in new window or tab >>Adhesive Wafer Bonding for Heterogeneous System Integration
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2018 (English)In: ECS Meeting Abstracts / [ed] The Electrochemical Society, 2018Conference paper, Oral presentation with published abstract (Refereed)
Keywords
Adhesive wafer bonding, Wafer bonding, Integration, Hetergeneous integration, MEMS, NEMS, CMOS
National Category
Manufacturing, Surface and Joining Technology Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-253894 (URN)
Conference
Americas International Meeting on Electrochemistry and Solid State Science (AiMES 2018)
Note

QC 20190624

Available from: 2019-06-19 Created: 2019-06-19 Last updated: 2019-06-24Bibliographically approved
Dubois, V. J., Bleiker, S. J., Stemme, G. & Niklaus, F. (2018). Scalable Manufacturing of Nanogaps. Advanced Materials, 30(46), Article ID 1801124.
Open this publication in new window or tab >>Scalable Manufacturing of Nanogaps
2018 (English)In: Advanced Materials, ISSN 0935-9648, E-ISSN 1521-4095, Vol. 30, no 46, article id 1801124Article, review/survey (Refereed) Published
Abstract [en]

The ability to manufacture a nanogap in between two electrodes has proven a powerful catalyst for scientific discoveries in nanoscience and molecular electronics. A wide range of bottom-up and top-down methodologies are now available to fabricate nanogaps that are less than 10 nm wide. However, most available techniques involve time-consuming serial processes that are not compatible with large-scale manufacturing of nanogap devices. The scalable manufacturing of sub-10 nm gaps remains a great technological challenge that currently hinders both experimental nanoscience and the prospects for commercial exploitation of nanogap devices. Here, available nanogap fabrication methodologies are reviewed and a detailed comparison of their merits is provided, with special focus on large-scale and reproducible manufacturing of nanogaps. The most promising approaches that could achieve a breakthrough in research and commercial applications are identified. Emerging scalable nanogap manufacturing methodologies will ultimately enable applications with high scientific and societal impact, including high-speed whole genome sequencing, electromechanical computing, and molecular electronics using nanogap electrodes.

Place, publisher, year, edition, pages
Wiley-VCH Verlagsgesellschaft, 2018
Keywords
break junctions, crack junctions, nanogap electrodes, parallel fabrication, wafer scale
National Category
Other Engineering and Technologies not elsewhere specified
Identifiers
urn:nbn:se:kth:diva-240766 (URN)10.1002/adma.201801124 (DOI)000453355300001 ()30156331 (PubMedID)2-s2.0-85052216514 (Scopus ID)
Note

QC 20190107

Available from: 2019-01-07 Created: 2019-01-07 Last updated: 2019-01-07Bibliographically approved
Laakso, M. J., Bleiker, S. J., Liljeholm, J., Mårtensson, G. E., Asiatici, M., Fischer, A. C., . . . Niklaus, F. (2018). Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires. IEEE Access, 6, 44306-44317
Open this publication in new window or tab >>Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires
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2018 (English)In: IEEE Access, E-ISSN 2169-3536, Vol. 6, p. 44306-44317Article in journal (Refereed) Published
Abstract [en]

A through-glass via (TGV) provides a vertical electrical connection through a glass substrate. TGVs are used in advanced packaging solutions, such as glass interposers and wafer-level packaging of microelectromechanical systems (MEMS). However, TGVs are challenging to realize because via holes in glass typically do not have a sufficiently high-quality sidewall profile for super-conformal electroplating of metal into the via holes. To overcome this problem, we demonstrate here that the via holes can instead be filled by magnetically assembling metal wires into them. This method was used to produce TGVs with a typical resistance of 64 m Omega, which is comparable with other metal TGV types reported in the literature. In contrast to many TGV designs with a hollow center, the proposed TGVs can be more area efficient by allowing solder bump placement directly on top of the TGVs, which was demonstrated here using solder-paste jetting. The magnetic assembly process can be parallelized using an assembly robot, which was found to provide an opportunity for increased wafer-scale assembly speed. The aforementioned qualities of the magnetically assembled TGVs allow the realization of glass interposers and MEMS packages in different thicknesses without the drawbacks associated with the current TGV fabrication methods.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
Chip scale packaging, femtosecond laser, glass interposer, laser ablation, multichip modules, robotic assembly, self-assembly, spin-on glass, thermal expansion, through-glass via, through-silicon vias, TSV
National Category
Communication Systems
Identifiers
urn:nbn:se:kth:diva-235465 (URN)10.1109/ACCESS.2018.2861886 (DOI)000444505800001 ()2-s2.0-85050982480 (Scopus ID)
Funder
Knut and Alice Wallenberg FoundationVINNOVA, 324189Swedish Foundation for Strategic Research , GMT14-0071 RIF14-0017
Note

QC 20180928

Available from: 2018-09-28 Created: 2018-09-28 Last updated: 2018-10-02Bibliographically approved
Laakso, M., Bleiker, S. J., Liljeholm, J., Mårtensson, G., Asiatici, M., Fischer, A. C., . . . Niklaus, F. (2018). Through-Glass Vias for MEMS Packaging. In: : . Paper presented at The Micronano System Workshop (MSW), 2018, Helsinki, Finland, 13-15 May.
Open this publication in new window or tab >>Through-Glass Vias for MEMS Packaging
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2018 (English)Conference paper, Oral presentation with published abstract (Other academic)
Abstract [en]

Novelty / Progress Claims We have developed a new method for fabrication of through-glass vias (TGVs). The method allows rapid filling of via holes with metal rods both in thin and thick glass substrates.

Background Vertical electrical feedthroughs in glass substrates, i.e. TGVs, are often required in wafer-scale packaging of MEMS that utilizes glass lids. The current methods of making TGVs have drawbacks that prevent the full utilization of the excellent properties of glass as a package material, e.g. low RF losses. Magnetic assembly has been used earlier to fabricate through-silicon vias (TSVs), and in this work we extend this method to realize TGVs [1].

Methods The entire TGV fabrication process is maskless, and the processes used include: direct patterning of wafer metallization using femtosecond laser ablation, magnetic-fieldassisted self-assembly of metal wires into via holes, and solder-paste jetting of bump bonds on TGVs.

Results We demonstrate that: (1) the magnetically assembled TGVs have a low resistance, which makes them suitable even for low-loss and high-current applications; (2) the magneticassembly process can be parallelized in order to increase the wafer-scale fabrication speed; (3) the magnetic assembly produces void-free metal filling for TGVs, which allows solder placement directly on top of the TGV for the purpose of high integration density; and (4) good thermal-expansion compatibility between TGV metals and glass substrates is possible with the right choice of materials, and several suitable metals-glass pairs are identified for possible improvement of package reliability [2].

[1] M. Laakso et al., IEEE 30th Int. Conf. on MEMS, 2017. DOI:10.1109/MEMSYS.2017.7863517

[2] M. Laakso et al., “Through-Glass Vias for Glass Interposers and MEMS Packaging Utilizing Magnetic Assembly of Microscale Metal Wires,” manuscript in preparatio

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-238647 (URN)
Conference
The Micronano System Workshop (MSW), 2018, Helsinki, Finland, 13-15 May
Note

QC 20181106

Available from: 2018-11-06 Created: 2018-11-06 Last updated: 2019-05-17Bibliographically approved
Wang, X., Bleiker, S. J., Antelius, M., Stemme, G. & Niklaus, F. (2017). Narrow footprint copper sealing rings for low-temperature hermetic wafer-level packaging. In: TRANSDUCERS 2017 - 19th International Conference on Solid-State Sensors, Actuators and Microsystems: . Paper presented at 19th International Conference on Solid-State Sensors, Actuators and Microsystems, TRANSDUCERS 2017, 18 June 2017 through 22 June 2017 (pp. 423-426). Institute of Electrical and Electronics Engineers (IEEE), Article ID 7994077.
Open this publication in new window or tab >>Narrow footprint copper sealing rings for low-temperature hermetic wafer-level packaging
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2017 (English)In: TRANSDUCERS 2017 - 19th International Conference on Solid-State Sensors, Actuators and Microsystems, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 423-426, article id 7994077Conference paper, Published paper (Refereed)
Abstract [en]

This paper reports a narrow footprint sealing ring design for low-temperature, hermetic, and mechanically stable wafer-level packaging. Copper (Cu) sealing rings that are as narrow as 8 μm successfully seal the enclosed cavities on the wafers after bonding at a temperature of 250 °C. Different sealing structure designs are evaluated and demonstrate excellent hermeticity after 3 months of storage in ambient atmosphere. A leak rate of better than 3.6×10'16 mbarL/s is deduced based on results from residual gas analysis measurements. The sealing yield after wafer bonding is found to be not limited by the Cu sealing ring width but by a maximum acceptable wafer-to-wafer misalignment.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2017
Keywords
Actuators, Copper, Electronics packaging, Microsystems, Sealing (closing), Solid-state sensors, Temperature, Transducers, Ambient atmosphere, Hermeticity, Low temperatures, Mechanically stable, Residual gas analysis, Sealing ring, Sealing structures, Wafer level packaging, Wafer bonding
National Category
Other Chemistry Topics
Identifiers
urn:nbn:se:kth:diva-216276 (URN)10.1109/TRANSDUCERS.2017.7994077 (DOI)000426701400105 ()2-s2.0-85029393420 (Scopus ID)9781538627310 (ISBN)
Conference
19th International Conference on Solid-State Sensors, Actuators and Microsystems, TRANSDUCERS 2017, 18 June 2017 through 22 June 2017
Note

QC 20171215

Available from: 2017-12-15 Created: 2017-12-15 Last updated: 2018-04-17Bibliographically approved
Bleiker, S. J., Fischer, A. C. & Niklaus, F. (2016). High-speed Metal-filling of Through-Silicon Vias (TSVs) by Parallelized Magnetic Assembly of Micro-Wires. In: 2016 IEEE 29th International Conference on Micro Electro Mechanical Systems (MEMS): . Paper presented at 29th IEEE International Conference on Micro Electro Mechanical Systems, MEMS 2016, Shanghai, China, 24 January 2016 through 28 January 2016 (pp. 577-580). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>High-speed Metal-filling of Through-Silicon Vias (TSVs) by Parallelized Magnetic Assembly of Micro-Wires
2016 (English)In: 2016 IEEE 29th International Conference on Micro Electro Mechanical Systems (MEMS), Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 577-580Conference paper, Published paper (Refereed)
Abstract [en]

This work reports a parallelized magnetic assembly method for scalable and cost-effective through-silicon via (TSV) fabrication. Our fabrication approach achieves high throughput by utilizing multiple magnets below the substrate to assemble TSV structures on many dies in parallel. Experimental results show simultaneous filling of four arrays of TSVs on a single substrate, with 100 via-holes each, in less than 20 seconds. We demonstrate that increasing the degree of parallelization by employing more assembly magnets below the substrate has no negative effect on the TSV filling speed or yield, thus enabling scaled-up TSV fabrication on full wafer-level. This method shows potential for industrial application with an estimated throughput of more than 70 wafers per hour in one single fabrication module. Such a TSV fabrication process could offer shorter processing times as well as higher obtainable aspect ratios compared to conventional TSV filling methods.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2016
Series
Proceedings IEEE Micro Electro Mechanical Systems, ISSN 1084-6999
Keywords
TSV, magnetic assembly
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-184232 (URN)10.1109/MEMSYS.2016.7421691 (DOI)000381797300151 ()2-s2.0-84971001486 (Scopus ID)978-1-5090-1973-1 (ISBN)
Conference
29th IEEE International Conference on Micro Electro Mechanical Systems, MEMS 2016, Shanghai, China, 24 January 2016 through 28 January 2016
Funder
EU, European Research Council, 277879VINNOVA, 324189
Note

QC 20161019

Available from: 2016-03-30 Created: 2016-03-30 Last updated: 2017-05-11Bibliographically approved
Bleiker, S. J., Fischer, A. C., Shah, U., Somjit, N., Haraldsson, T., Roxhed, N., . . . Niklaus, F. (2015). High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires. IEEE Transactions on Components, Packaging, and Manufacturing Technology, 5(1), 21-27
Open this publication in new window or tab >>High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires
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2015 (English)In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 5, no 1, p. 21-27Article in journal (Refereed) Published
Abstract [en]

In this paper, we demonstrate a novel manufacturing technology for high-aspect-ratio vertical interconnects for high-frequency applications. This novel approach is based on magnetic self-assembly of prefabricated nickel wires that are subsequently insulated with a thermosetting polymer. The high-frequency performance of the through silicon vias (TSVs) is enhanced by depositing a gold layer on the outer surface of the nickel wires and by reducing capacitive parasitics through a low-k polymer liner. As compared with conventional TSV designs, this novel concept offers a more compact design and a simpler, potentially more cost-effective manufacturing process. Moreover, this fabrication concept is very versatile and adaptable to many different applications, such as interposer, micro electromechanical systems, or millimeter wave applications. For evaluation purposes, coplanar waveguides with incorporated TSV interconnections were fabricated and characterized. The experimental results reveal a high bandwidth from dc to 86 GHz and an insertion loss of <0.53 dB per single TSV interconnection for frequencies up to 75 GHz.

Place, publisher, year, edition, pages
IEEE Press, 2015
Keywords
RF signal transmission, skin effect, through silicon via (TSV), vertical interconnection, wafer scale integration
National Category
Materials Engineering
Identifiers
urn:nbn:se:kth:diva-160401 (URN)10.1109/TCPMT.2014.2369236 (DOI)000348123200004 ()2-s2.0-84921411485 (Scopus ID)
Funder
Swedish Research Council, 277879
Note

QC 20150224

Available from: 2015-02-24 Created: 2015-02-19 Last updated: 2017-12-04Bibliographically approved
Fischer, A. C., Forsberg, F., Lapisa, M., Bleiker, S. J., Stemme, G., Roxhed, N. & Niklaus, F. (2015). Integrating MEMS and ICs [Review]. Microsystems & Nanoengineering, 1(1), 1-16, Article ID 15005.
Open this publication in new window or tab >>Integrating MEMS and ICs
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2015 (English)In: Microsystems & Nanoengineering, ISSN 2055-7434, Vol. 1, no 1, p. 1-16, article id 15005Article, book review (Refereed) Published
Abstract [en]

The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the ‘More-Than-Moore’ paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated. The implications of the different MEMS and IC integration approaches for packaging, testing and final system costs are reviewed.

Keywords
Cofabrication platforms, integrated circuits (ICs), microelectromechanical system (MEMS), More-Than-Moore, multichip modules (MCMs), system-in-package (SiP), system-on-chip (SoC), three-dimensional (3D) heterogeneous integration
National Category
Natural Sciences Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-169103 (URN)10.1038/micronano.2015.5 (DOI)000218367600021 ()2-s2.0-85045082677 (Scopus ID)
Note

QC 20150618

Available from: 2015-06-11 Created: 2015-06-11 Last updated: 2019-09-30Bibliographically approved
Ayala, C. L., Grogg, D., Bazigos, A., Bleiker, S. J., Fernandez-Bolanos, M., Niklaus, F. & Hagleitner, C. (2015). Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts. Paper presented at 44th European Solid-State Device Research Conference (ESSDERC), SEP 22-26, 2014, Venice, ITALY. Solid-State Electronics, 113, 157-166
Open this publication in new window or tab >>Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts
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2015 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 113, p. 157-166Article in journal (Refereed) Published
Abstract [en]

Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 mu m x 10 mu m using 6 NEM switches. Each NEM switch device has a footprint of 5 mu m x 3 mu m, an air gap of 60 mu m and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.

Keywords
NEMS, Ring oscillator, VLSI, Digital logic design, Curved cantilever, Amorphous carbon
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-173125 (URN)10.1016/j.sse.2015.05.029 (DOI)000359170600026 ()2-s2.0-84937250804 (Scopus ID)
Conference
44th European Solid-State Device Research Conference (ESSDERC), SEP 22-26, 2014, Venice, ITALY
Note

QC 20150918

Available from: 2015-09-18 Created: 2015-09-07 Last updated: 2018-04-11Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-4867-0391

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