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Salemi, A., Elahipanah, H., Jacobs, K., Zetterling, C.-M. & Östling, M. (2018). 15 kV-Class Implantation-Free 4H-SiC BJTs With Record High Current Gain. IEEE Electron Device Letters, 39(1), 63-66
Open this publication in new window or tab >>15 kV-Class Implantation-Free 4H-SiC BJTs With Record High Current Gain
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2018 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 1, p. 63-66Article in journal (Refereed) Published
Abstract [en]

Implantation-free mesa-etched ultra-high-voltage (0.08 mm(2)) 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured, and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension is utilized to obtain a high and stable breakdown voltage without ion implantation. The open-base blocking voltage of 15.8 kV at a leakage current density of 0.1 mA/cm(2) is achieved. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
Ultra-high-voltage 4H-SiC BJT, implantation-free, area-optimized junction termination extension (O-JTE), current gain, on-resistance, optimal cell geometries, surface passivation
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-220997 (URN)10.1109/LED.2017.2774139 (DOI)000418874200016 ()2-s2.0-85036592983 (Scopus ID)
Funder
StandUpSwedish Energy Agency
Note

QC 20180111

Available from: 2018-01-11 Created: 2018-01-11 Last updated: 2018-01-11Bibliographically approved
Salemi, A., Elahipanah, H., Zetterling, C.-M. & Östling, M. (2018). Conductivity modulated and implantation-free 4H-SiC ultra-high-voltage PiN Diodes. In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017: . Paper presented at 17 September 2017 through 22 September 2017 (pp. 568-572). Trans Tech Publications Inc.
Open this publication in new window or tab >>Conductivity modulated and implantation-free 4H-SiC ultra-high-voltage PiN Diodes
2018 (English)In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications Inc., 2018, p. 568-572Conference paper, Published paper (Refereed)
Abstract [en]

Implantation-free mesa etched ultra-high-voltage 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. The diode’s design allows a high breakdown voltage of about 19.3 kV according to simulations. No reverse breakdown is observed up to 13 kV with a very low leakage current of 0.1 μA. A forward voltage drop (VF) and differential on-resistance (Diff. Ron) of 9.1 V and 41.4 mΩ cm2 are measured at 100 A/cm2, respectively, indicating the effect of conductivity modulation.

Place, publisher, year, edition, pages
Trans Tech Publications Inc., 2018
Keywords
4H-SiC PiN diode, Conductivity modulation, Differential on-resistance, Forward voltage drop, Implantation-free, Ultra-high-voltage, Diodes, Heterojunction bipolar transistors, Leakage currents, Modulation, Nitrogen compounds, Semiconductor junctions, Silicon carbide, Forward voltage drops, On-resistance, SiC PiN diodes, Ultra high voltage, Power semiconductor diodes
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-236358 (URN)10.4028/www.scientific.net/MSF.924.568 (DOI)2-s2.0-85049010479 (Scopus ID)9783035711455 (ISBN)
Conference
17 September 2017 through 22 September 2017
Note

QC 20181106

Available from: 2018-11-06 Created: 2018-11-06 Last updated: 2018-11-06Bibliographically approved
Ekström, M., Hou, S., Elahipanah, H., Salemi, A., Östling, M. & Zetterling, C.-M. (2018). Low temperature Ni-Al ohmic contacts to p-TYPE 4H-SiC using semi-salicide processing. In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017: . Paper presented at International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Columbia, United States, 17 September 2017 through 22 September 2017 (pp. 389-392). Trans Tech Publications, 924
Open this publication in new window or tab >>Low temperature Ni-Al ohmic contacts to p-TYPE 4H-SiC using semi-salicide processing
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2018 (English)In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, Vol. 924, p. 389-392Conference paper, Published paper (Refereed)
Abstract [en]

Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10-4 Ω cm2) to epitaxially grown p-type (>5×1018 cm-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni2Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.

Place, publisher, year, edition, pages
Trans Tech Publications, 2018
Series
Materials Science Forum, ISSN 0255-5476 ; 924
Keywords
Ni-Al, P-type ohmic contact, Rapid thermal processing (RTP), Silicon carbide (4H-SiC), Transfer length method (TLM)
National Category
Other Engineering and Technologies
Identifiers
urn:nbn:se:kth:diva-238393 (URN)10.4028/www.scientific.net/MSF.924.389 (DOI)2-s2.0-85049019579 (Scopus ID)9783035711455 (ISBN)
Conference
International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Columbia, United States, 17 September 2017 through 22 September 2017
Note

QC 20181108

Available from: 2018-11-08 Created: 2018-11-08 Last updated: 2019-04-29Bibliographically approved
Salemi, A., Elahipanah, H., Zetterling, C.-M. & Östling, M. (2017). 10+ kV implantation-free 4H-SiC PiN diodes. In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016: . Paper presented at 25 September 2016 through 29 September 2016 (pp. 423-426). Trans Tech Publications Ltd
Open this publication in new window or tab >>10+ kV implantation-free 4H-SiC PiN diodes
2017 (English)In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016, Trans Tech Publications Ltd , 2017, p. 423-426Conference paper (Refereed)
Abstract [en]

Implantation-free mesa etched 10+ kV 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. An area-optimized junction termination extension (O-JTE) is implemented in order to achieve a high breakdown voltage. The diodes design allows a high breakdown voltage of about 19.3 kV according to simulations by Sentaurus TCAD. No breakdown voltage is recorded up to 10 kV with a very low leakage current of 0.1 μA. The current spreading within the thick drift layer is considered and a voltage drop (VF) of 8.3 V and 11.4 V are measured at 50 A/cm2 and 100 A/cm2, respectively. The differential on-resistance (Diff. Ron) of 67.7 mΩ.cm2 and 55.7 mΩ.cm2 are measured at 50 A/cm2 and 100 A/cm2, respectively.

Place, publisher, year, edition, pages
Trans Tech Publications Ltd, 2017
Keywords
Conductivity modulation, Differential on-resistance, Forward voltage drop, Implantation-free, PiN diode, Ultra-high-voltage
National Category
Materials Engineering
Identifiers
urn:nbn:se:kth:diva-216561 (URN)10.4028/www.scientific.net/MSF.897.423 (DOI)2-s2.0-85019990289 (Scopus ID)9783035710434 (ISBN)
Conference
25 September 2016 through 29 September 2016
Note

QC 20171108

Available from: 2017-11-08 Created: 2017-11-08 Last updated: 2017-11-08Bibliographically approved
Elahipanah, H., Kargarrazi, S., Salemi, A., Östling, M. & Zetterling, C.-M. (2017). 500 degrees C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits. IEEE Electron Device Letters, 38(10), 1429-1432
Open this publication in new window or tab >>500 degrees C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits
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2017 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 38, no 10, p. 1429-1432Article in journal (Refereed) Published
Abstract [en]

High-current 4H-SiC lateral BJTs for hightemperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (J(C)), lower on-resistance (R-ON), and more uniform current distribution. A maximum current gain (beta) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs aremeasured fromroom temperature to 500 degrees C. An open-base breakdown voltage (V-CEO) of > 50 V is measured for the devices.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2017
Keywords
4H-SiC, lateral BJT, high-current, monolithic integrated circuit
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-217444 (URN)10.1109/LED.2017.2737558 (DOI)000413760600019 ()
Note

QC 20171117

Available from: 2017-11-17 Created: 2017-11-17 Last updated: 2017-11-17Bibliographically approved
Elahipanah, H., Asadollahi, A., Ekström, M., Salemi, A., Zetterling, C.-M. & Östling, M. (2017). A wafer-scale Ni-salicide contact technology on n-type 4H-SiC. ECS Journal of Solid State Science and Technology, 6(4), P197-P200
Open this publication in new window or tab >>A wafer-scale Ni-salicide contact technology on n-type 4H-SiC
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2017 (English)In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 4, p. P197-P200Article in journal (Refereed) Published
Abstract [en]

A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10−6 Ω · cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.

Place, publisher, year, edition, pages
Electrochemical Society, 2017
National Category
Other Engineering and Technologies
Identifiers
urn:nbn:se:kth:diva-219898 (URN)10.1149/2.0041705jss (DOI)000418886800004 ()2-s2.0-85036466021 (Scopus ID)
Note

QC 20171215

Available from: 2017-12-15 Created: 2017-12-15 Last updated: 2018-01-11Bibliographically approved
Malm, B. G., Elahipanah, H., Salemi, A. & Östling, . (2017). Gated base structure for improved current gain in SiC bipolar technology. In: 2017 47th European Solid-State Device Research Conference (ESSDERC) 11-14 Sept. 2017: . Paper presented at 47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, 11 September 2017 through 14 September 2017 (pp. 122-125). Editions Frontieres
Open this publication in new window or tab >>Gated base structure for improved current gain in SiC bipolar technology
2017 (English)In: 2017 47th European Solid-State Device Research Conference (ESSDERC) 11-14 Sept. 2017, Editions Frontieres , 2017, p. 122-125Conference paper (Refereed)
Abstract [en]

Silicon Carbide (SiC) bipolar integrated circuits are a promising technology for extreme environment applications. SiC bipolar technology shows stable operation over a wide range of temperature. However, the current gain of the devices is suffering from high surface recombination, due to poor oxide passivation. In this paper we propose a gated base structure that offers improved current gain control. A polysilicon gate is formed on the passivation oxide on top of the base-link region. We investigate the current gain as a function of gate bias and temperature. A negative gate bias improves the gain at low collector current by more than 30% by suppressing the surface recombination. Measurements are presented at temperatures ranging from 300 K to 550 K and the gain is consistently improved. The proposed structure is also useful as a process monitor for the passivation oxide quality.

Place, publisher, year, edition, pages
Editions Frontieres, 2017
Series
European Solid-State Device Research Conference, ISSN 1930-8876
Keywords
bipolar, current gain, extreme enviroment, process monitor, silicon carbide (SiC), surface passivation, test structure
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-218127 (URN)10.1109/ESSDERC.2017.8066607 (DOI)2-s2.0-85033444950 (Scopus ID)9781509059782 (ISBN)
Conference
47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, 11 September 2017 through 14 September 2017
Note

QC 20171123

Available from: 2017-11-23 Created: 2017-11-23 Last updated: 2017-11-23Bibliographically approved
Salemi, A., Elahipanah, H., Zetterling, C.-M. & Östling, M. (2016). Geometrical effect dependency on the on-state characteristics in 5.6 kV 4H-SiC BJTs. In: 16th International Conference on Silicon Carbide and Related Materials, ICSCRM 2015: . Paper presented at 4 October 2015 through 9 October 2015 (pp. 958-961). Trans Tech Publications Ltd
Open this publication in new window or tab >>Geometrical effect dependency on the on-state characteristics in 5.6 kV 4H-SiC BJTs
2016 (English)In: 16th International Conference on Silicon Carbide and Related Materials, ICSCRM 2015, Trans Tech Publications Ltd , 2016, p. 958-961Conference paper, Published paper (Refereed)
Abstract [en]

The influence of varying the emitter-base geometry, i.e., the emitter width (WE), emitter contact-emitter edge distance (Wn), and base contact-emitter edge (Wp) on the on-state characteristics in 5.6 kV implantation free 4H-SiC BJTs is investigated. The BJTs present a clear emitter size effect pointing out that surface recombination has a significant influence on current gain (β). The results show that the influence of varying Wp on the β is higher than Wn. A distance of 3 μm between emitter contact and base contact to the emitter edge (Wn = Wp = 3 μm) is the optimized value to have a BJT with a high β, and low on-resistance (RON) at a given WE.

Place, publisher, year, edition, pages
Trans Tech Publications Ltd, 2016
Keywords
Bipolar junction transistor (BJT), Current density, Current gain, Implantation free, On-resistance, Silicon carbide (SiC), Bipolar transistors, Semiconductor junctions, Silicon, Silicon carbide, State estimation, Current gains, Emitter edges, Emitter-size effect, Geometrical effect, On currents, Silicon carbides (SiC), Surface recombinations, Power bipolar transistors
National Category
Materials Engineering
Identifiers
urn:nbn:se:kth:diva-195482 (URN)10.4028/www.scientific.net/MSF.858.958 (DOI)2-s2.0-84971525103 (Scopus ID)9783035710427 (ISBN)
Conference
4 October 2015 through 9 October 2015
Note

QC 20161125

Available from: 2016-11-25 Created: 2016-11-03 Last updated: 2016-11-25Bibliographically approved
Moeen, M., Kolahdouz, M. R., Salemi, A., Östling, M. & Radamson, H. (2016). Improved designs of Si-based quantum wells and Schottky diodes for IR detection. Paper presented at E-MRS Symposium K on Transport and Photonics in Group IV based Nano-Devices, May, 2015, Lille, France. Thin Solid Films, 613, 19-23
Open this publication in new window or tab >>Improved designs of Si-based quantum wells and Schottky diodes for IR detection
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2016 (English)In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 613, p. 19-23Article in journal (Refereed) Published
Abstract [en]

Novel structures of intrinsic or carbon-doped multi quantum wells (MQWs) and intrinsic or carbon-doped Si Schottky diodes (SD), individually or in combination, have been manufactured to detect the infrared (IR) radiation. The carbon concentration in the structures was 5 × 1020 cm− 3 and the MQWs are located in the active part of the IR detector. A Schottky diode was designed and formed as one of the contacts (based on NiSi(C)/TiW) to MQWs where on the other side the structure had an Ohmic contact. The thermal response of the detectors is expressed in terms of temperature coefficient of resistance (TCR) and the quality of the electrical signal is quantified by the signal-to-noise ratio. The noise measurements provide the K1/f parameter which is obtained from the power spectrum density. An excellent value of TCR = − 6%/K and K1/f = 4.7 × 10− 14 was measured for the detectors which consist of the MQWs in series with the SD. These outstanding electrical results indicate a good opportunity to manufacture low cost Si-based IR detectors in the near future.

Place, publisher, year, edition, pages
Elsevier, 2016
Keywords
Infrared, Infrared detection, Silicon germanium, Bolometers, Noise measurement
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-185460 (URN)10.1016/j.tsf.2016.02.003 (DOI)000381031000003 ()
Conference
E-MRS Symposium K on Transport and Photonics in Group IV based Nano-Devices, May, 2015, Lille, France
Note

QC 20160915

Available from: 2016-04-19 Created: 2016-04-19 Last updated: 2017-11-30Bibliographically approved
Radamson, H., Moeen, M., Abedin, A., Salemi, A. & Kolahdouzb, M. (2016). Sensitivity of Signal-to-Noise Ratio to the Layer Profile and Crystal Quality of SiGe/Si Multilayers. ECS Journal of Solid State Science and Technology, 5, 3196-3201
Open this publication in new window or tab >>Sensitivity of Signal-to-Noise Ratio to the Layer Profile and Crystal Quality of SiGe/Si Multilayers
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2016 (English)In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 5, p. 3196-3201Article in journal, Editorial material (Other (popular science, discussion, etc.)) Published
Abstract [en]

This study presents signal-to-noise ratio (SNR) measurements of single crystalline dots or layers of SiGe/Si in multilayer structures in terms of Ge content, interfacial and layer quality. All multilayers were processed in form of mesas and the noise behavior of electrical signal was investigated by comparing the power spectral density curves and K1/f values. The SiGe/Si multilayer structures were also characterized by the conventional material analysis tools and the results were compared to the noise measurements. The quality of SiGe/Si interface or SiGe layer was monitored by intentional exposure to oxygen in range of 2–1600 nTorr either during or prior to SiGe growth. The results demonstrated that SNR was sensitive to the interfacial and layer quality, and the Ge content in a multilayer structure. The noise level became very high when the strain fluctuated within SiGe layer and this occurred for SiGe with high Ge content or SiGe dots.

Place, publisher, year, edition, pages
Electrochemical Society, 2016
National Category
Materials Engineering Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-185459 (URN)10.1149/2.0261604jss (DOI)000373212500027 ()
Note

QC 20160823

Available from: 2016-04-19 Created: 2016-04-19 Last updated: 2017-08-16Bibliographically approved
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Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-7510-9639

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