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Garidis, KonstantinosORCID iD iconorcid.org/0000-0003-0568-0984
Publications (9 of 9) Show all publications
Abedin, A., Zurauskaite, L., Asadollahi, A., Garidis, K., Jayakumar, G., Malm, B. G., . . . Östling, M. (2018). Germanium on Insulator Fabrication for Monolithic 3-D Integration. IEEE Journal of the Electron Devices Society, 6(1), 588-593
Open this publication in new window or tab >>Germanium on Insulator Fabrication for Monolithic 3-D Integration
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2018 (English)In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed) Published
Abstract [en]

A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018
Keywords
GOI, wafer bonding, selective etching, GOI MOSFET, 3D integration
National Category
Materials Chemistry
Identifiers
urn:nbn:se:kth:diva-231645 (URN)10.1109/JEDS.2018.2801335 (DOI)000435505000007 ()2-s2.0-85041650674 (Scopus ID)
Funder
Swedish Foundation for Strategic Research
Note

QC 20180904

Available from: 2018-09-04 Created: 2018-09-04 Last updated: 2018-10-19Bibliographically approved
Abedin, A., Zurauskaite, L., Asadollahi, A., Garidis, K., Jayakumar, G., Malm, B. G., . . . Östling, M. (2018). GOI fabrication for monolithic 3D integration. In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017: . Paper presented at 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Hyatt Regency San Francisco Airport Hotel Burlingame, United States, 16 October 2017 through 18 October 2017 (pp. 1-3). Institute of Electrical and Electronics Engineers (IEEE), 2018
Open this publication in new window or tab >>GOI fabrication for monolithic 3D integration
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2018 (English)In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper, Published paper (Refereed)
Abstract [en]

A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
3D Integration, GOI, GOI MOSFET, Selective Etching, Wafer Bonding
National Category
Other Engineering and Technologies
Identifiers
urn:nbn:se:kth:diva-230046 (URN)10.1109/S3S.2017.8309201 (DOI)2-s2.0-85047768082 (Scopus ID)9781538637654 (ISBN)
Conference
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Hyatt Regency San Francisco Airport Hotel Burlingame, United States, 16 October 2017 through 18 October 2017
Note

QC 20180611

Available from: 2018-06-11 Created: 2018-06-11 Last updated: 2018-06-11Bibliographically approved
Abedin, A., Asadollahi, A., Garidis, K., Hellström, P.-E. & Östling, M. (2016). Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density. In: ECS Transactions: . Paper presented at Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016 (pp. 615-621). Electrochemical Society (8)
Open this publication in new window or tab >>Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density
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2016 (English)In: ECS Transactions, Electrochemical Society, 2016, no 8, p. 615-621Conference paper, Published paper (Refereed)
Abstract [en]

Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

Place, publisher, year, edition, pages
Electrochemical Society, 2016
Keywords
Chemical vapor deposition, Silicon, Silicon alloys, Strain relaxation, Surface defects, Surface roughness, Surface topography, Temperature, Defects density, Low-dislocation density, Low-temperature grown, Mobility enhancement, Reduced pressure chemical vapor deposition, Strain relaxed buffers, Strain-relaxed, Threading dislocation densities, Germanium
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-201995 (URN)10.1149/07508.0615ecst (DOI)2-s2.0-84991585471 (Scopus ID)9781607685395 (ISBN)
Conference
Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016
Note

QC 20170224

Available from: 2017-02-24 Created: 2017-02-24 Last updated: 2018-01-15Bibliographically approved
Garidis, K., Jayakumar, G., Asadollahi, A., Dentoni Litta, E., Hellström, P.-E. & Östling, M. (2015). Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration. In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon: . Paper presented at 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015; Bologna; Italy; 26 January 2015 through 28 January 2015 (pp. 165-168).
Open this publication in new window or tab >>Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration
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2015 (English)In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015, p. 165-168Conference paper, Published paper (Refereed)
Abstract [en]

We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C-350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.

Keywords
3D integration, atomic layer deposition, current leakage, defects, Ge, GeOI, inter layer dielectrics, monolithic, strained Ge, wafer bonding, Deposition, Germanium, Integration, Leakage (fluid), Monolithic integrated circuits, Silicon wafers, Surface roughness, Three dimensional integrated circuits, 3-D integration, Inter-layer dielectrics, Strained-Ge
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-167390 (URN)10.1109/ULIS.2015.7063799 (DOI)000380427400042 ()2-s2.0-84926444085 (Scopus ID)9781479969111 (ISBN)
External cooperation:
Conference
2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015; Bologna; Italy; 26 January 2015 through 28 January 2015
Note

QC 20150529

Available from: 2015-05-29 Created: 2015-05-22 Last updated: 2016-09-02Bibliographically approved
Jayakumar, G., Garidis, K., Hellstrom, P.-E. & Östling, M. (2014). Fabrication and characterization of silicon nanowires using STL for biosensing applications. Paper presented at 15th International Conference on Ultimate Integration on Silicon (ULIS), APR 07-09, 2014, Stockholm, SWEDEN. INT CONF ULTI INTEGR, 109-112
Open this publication in new window or tab >>Fabrication and characterization of silicon nanowires using STL for biosensing applications
2014 (English)In: INT CONF ULTI INTEGR, ISSN 2330-5738, p. 109-112Article in journal (Refereed) Published
Abstract [en]

We present a sidewall transfer lithography (STL) process to fabricate silicon nanowires using the CMOS compatible materials SiO2, SiN and alpha-Si. The STL process is implemented using a single cluster tool for reactive ion etching (RIE) and plasma enhanced chemical vapor deposition (PECVD) with a maximum process temperature of 400 degrees C. Using three lithography masks, single and multiple silicon nanowires connected to contact areas can be defined. By optimizing layer thicknesses, RIE and deposition conformity we demonstrate wafer scale definition of 60 nm wide silicon nanowires using I-line stepper lithography. The silicon nanowires exhibit excellent characteristics for biosensing applications with subthreshold slopes of 75 mV/dec and a high on/off current ratio of more than 10(5).

Keywords
nanowire, biosensing, SOI, CMOS, STL, step coverage, threshold voltage, subthreshold slope
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-153866 (URN)10.1109/ULIS.2014.6813928 (DOI)000341731300028 ()2-s2.0-84901357181 (Scopus ID)
Conference
15th International Conference on Ultimate Integration on Silicon (ULIS), APR 07-09, 2014, Stockholm, SWEDEN
Note

QC 20141009

Available from: 2014-10-09 Created: 2014-10-09 Last updated: 2014-10-09Bibliographically approved
Jayakumar, G., Asadollahi, A., Hellström, P.-E., Garidis, K. & Östling, M. (2014). Silicon nanowires integrated with CMOS circuits for biosensing application. Solid-State Electronics, 98, 26-31
Open this publication in new window or tab >>Silicon nanowires integrated with CMOS circuits for biosensing application
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2014 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 98, p. 26-31Article in journal (Refereed) Published
Abstract [en]

We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N-2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

Keywords
Nanowire, Biosensing, SOI, CMOS, STL
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-149200 (URN)10.1016/j.sse.2014.04.005 (DOI)000339149000006 ()2-s2.0-84902251547 (Scopus ID)
Funder
EU, European Research Council, 228229
Note

QC 20140818

Available from: 2014-08-18 Created: 2014-08-18 Last updated: 2018-01-15Bibliographically approved
Pret, A. V., Gronheid, R., Engelen, J., Yan, P.-Y., Leeson, M. J., Younkin, T. R., . . . Biafore, J. (2013). Mask Effects on Resist Variability in Extreme Ultraviolet Lithography. Japanese Journal of Applied Physics, 52(6), UNSP 06GC02
Open this publication in new window or tab >>Mask Effects on Resist Variability in Extreme Ultraviolet Lithography
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2013 (English)In: Japanese Journal of Applied Physics, ISSN 0021-4922, E-ISSN 1347-4065, Vol. 52, no 6, p. UNSP 06GC02-Article in journal (Refereed) Published
Abstract [en]

Resist variability is one of the challenges that must to be solved in extreme UV lithography. One of the root causes of the resist roughness are the mask contributions. Three different effects may plays a non-negligible role: mask pattern roughness transfer-or mask line edge roughness, speckle effects caused by mask surface roughness, and mask layout which causes local flare amplification at wafer level. In this paper, mask contributions to the pattern variability are individually assessed experimentally and via stochastic simulations for both lines/spaces and contact holes. It was found that the predominant effect is the mask layout, while the speckle contribution is barely detectable.

Keywords
Line-Edge Roughness, Metrics, Impact, UV
National Category
Other Physics Topics
Identifiers
urn:nbn:se:kth:diva-125763 (URN)10.7567/JJAP.52.06GC02 (DOI)000321059300007 ()2-s2.0-84881012036 (Scopus ID)
Note

QC 20130814

Available from: 2013-08-14 Created: 2013-08-13 Last updated: 2017-12-06Bibliographically approved
Jayakumar, G., Asadollahi, A., Hellström, P.-E., Garidis, K. & Östling, M. (2013). Silicon Nanowires Integrated in a Fully Depleted CMOS Process for Charge Based Biosensing. In: ULIS 2013: The 14th International Conference on Ultimate Integration on Silicon, Incorporating the 'Technology Briefing Day'. Paper presented at 14th International Conference on Ultimate Integration on Silicon (ULIS), MAR 19-21, 2013, Coventry, England (pp. 81-84). IEEE
Open this publication in new window or tab >>Silicon Nanowires Integrated in a Fully Depleted CMOS Process for Charge Based Biosensing
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2013 (English)In: ULIS 2013: The 14th International Conference on Ultimate Integration on Silicon, Incorporating the 'Technology Briefing Day', IEEE , 2013, p. 81-84Conference paper, Published paper (Refereed)
Abstract [en]

We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of 32 by 32 pixel matrix (1024 pixels or test sites) and 8 input-output (I/O) pins. In each pixel single crystalline SiNW with 60 by 20 nm cross-section area is defined using sidewall transfer lithography (STL) in the SOI layer. The key advantage of the design is that 1024 individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

Place, publisher, year, edition, pages
IEEE, 2013
Series
International Conference on Ultimate Integration on Silicon, ISSN 2330-5738
Keywords
nanowire, biosensing, SOI, CMOS, STL
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-133498 (URN)10.1109/ULIS.2013.6523496 (DOI)000325214300020 ()2-s2.0-84880273605 (Scopus ID)978-1-4673-4802-7 (ISBN)
Conference
14th International Conference on Ultimate Integration on Silicon (ULIS), MAR 19-21, 2013, Coventry, England
Note

QC 20131106

Available from: 2013-11-06 Created: 2013-11-06 Last updated: 2018-01-15Bibliographically approved
Garidis, K., Pret, A. V. & Gronheid, R. (2012). Mask roughness impact on extreme UV and 193 nm immersion lithography. Microelectronic Engineering, 98, 138-141
Open this publication in new window or tab >>Mask roughness impact on extreme UV and 193 nm immersion lithography
2012 (English)In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 98, p. 138-141Article in journal (Refereed) Published
Abstract [en]

The contribution of mask absorber line edge roughness on printed resist lines is studied for extreme UV and 193 nm immersion lithography. Programmed roughness modules were designed for roughness transfer function evaluation on 88 nm pitch line space patterns. The tested modules were designed applying variations of roughness amplitude and spatial frequency. Power spectral density analysis was performed on top-down SEM images. The effect of frequency roughness filtering by the lithographic optical system was studied with different illumination settings. It was found that, except for the degradation of the aerial image due to the filtering effect, less performing illuminations show an increased deterioration of the aerial image quality and thus contribute further to line edge roughness. A comparison with previous work was completed on different mask architectures and photoresist platforms. Resist performance can attenuate the roughness transfer from mask but at the cost of worse chemical gradient at the edges of the exposed regions.

Keywords
EUV, Frequency analysis, LER, LWR, Programmed roughness
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-103529 (URN)10.1016/j.mee.2012.07.068 (DOI)000309497200026 ()2-s2.0-84865608370 (Scopus ID)
Note

QC 20121017

Available from: 2012-10-17 Created: 2012-10-15 Last updated: 2017-12-07Bibliographically approved
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Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0003-0568-0984

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