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Jayakumar, G. & Östling, M. (2019). Pixel-based biosensor for enhanced control: silicon nanowires monolithically integrated with field-effect transistors in fully depleted silicon on insulator technology. Nanotechnology, 30(22), Article ID 225502.
Open this publication in new window or tab >>Pixel-based biosensor for enhanced control: silicon nanowires monolithically integrated with field-effect transistors in fully depleted silicon on insulator technology
2019 (English)In: Nanotechnology, ISSN 0957-4484, E-ISSN 1361-6528, Vol. 30, no 22, article id 225502Article in journal (Refereed) Published
Abstract [en]

Silicon nanowires (SiNWs) are a widely used technology for sensing applications. Complementary metal-oxide-semiconductor (CMOS) integration of SiNWs advances lab-on-chip (LOC) technology and offers opportunities for read-out circuit integration, selective and multiplexed detection. In this work, we propose novel scalable pixel-based biosensors exploiting the integration of SiNWs with CMOS in fully-depleted silicon-on-insulator technology. A detailed description of the wafer-scale fabrication of SiNW pixels using the CMOS compatible sidewall-transfer-lithography as an alternative to widely investigated time inefficient e-beam lithography is presented. Each 60 nm wide SiNWs sensor is monolithically connected to a control transistor and novel on-chip fluid-gate forming an individual pixel that can be operated in two modes: biasing transistor frontgate (V-G) or substrate backgate (V-BG). We also present the first electrical results of single N and P-type SiNW pixels. In frontgate mode, N and P-type SiNW pixels exhibit subthreshold slope (SS) approximate to 70-80 mV/dec and I-on/I-off approximate to 10(5). The N-type and P-type pixels have an average threshold voltage, Vth of -1.7 V and 0.85 V respectively. In the backgate mode, N and P-type SiNW pixels exhibit SS approximate to 100-150 mV/dec and I-on/I-off approximate to 10(6). The N and P-type pixels have an average V-th of 5 V and -2.5 V respectively. Further, the influence of the backgate and frontgate voltage on the switching characteristics of the SiNW pixels is also studied. In the frontgate mode, the Vth of the SiNW pixels can be tuned at 0.2 V for 1 V change in V-BG for N-type or at -0.2 V for -1 V change in V-BG for P-type pixels. In the backgate mode, it is found that for stable operation of the pixels, the V-G of the N and P-type transistors must be in the range 0.5-2.5 V and 0 V to -2.5 V respectively.

Place, publisher, year, edition, pages
IOP PUBLISHING LTD, 2019
Keywords
silicon nanowire pixel; silicon nanowire biosensor; lab-on-chip; SiNW CMOS integration; selective multiplexed detection; SiNW frontgate mode; SiNW backgate mode
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-248056 (URN)10.1088/1361-6528/ab0469 (DOI)000461650400002 ()30721898 (PubMedID)2-s2.0-85063252229 (Scopus ID)
Note

QC 20190429

Available from: 2019-04-29 Created: 2019-04-29 Last updated: 2019-04-29Bibliographically approved
Jayakumar, G., Hellström, P.-E. & Östling, M. (2019). Utilizing the superior etch stop quality of HfO 2 in the front end of line wafer scale integration of silicon nanowire biosensors. Microelectronic Engineering, 212, 13-20
Open this publication in new window or tab >>Utilizing the superior etch stop quality of HfO 2 in the front end of line wafer scale integration of silicon nanowire biosensors
2019 (English)In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 212, p. 13-20Article in journal (Refereed) Published
Abstract [en]

Silicon nanowire (SiNW) biosensors have received a special attention from the research community due to its ability to detect a range of species. The nano feature size of the SiNW has been exploited to fabricate small, low-cost, robust, portable, real-time read-out biosensors. These sensors are manufactured by two methods – top-down or bottom-up. Instead of the bottom-up method, the top-down approach is widely used due to its compatibility with complementary metal-oxide semiconductor (CMOS) process and scope of mass production. However, in the top-down method, the post fabrication microfluidic channel integration to access the SiNW test site remains complex and challenging. Since the nanosensor is expected to operate in a bio environment, it is essential to passivate the metal electrodes while pathways have to be made to access the test site. In this paper, we present a relatively easier method to access the SiNW test site without employing complex microfluidic channels while achieving leakage free passivation of metal electrodes and preserving the integrity of the nanosensor. This is accomplished in the last step of the manufacturing process by employing a lithography mask and reactive ion etching (RIE). HfO 2 integrated crystalline silicon nanosensors are manufactured using novel top-down front end of line (FEOL) sidewall transfer lithography (STL) process. HfO 2 acts as an etch stop layer while performing RIE in the last step to access the sensor test site. The 100 mm wafer scale results of 20 nm × 60 nm × 6 μm (H x W x L) p-type nanosensors shows an average I on /I off ≥ 10 5 with maximum turn-on voltage of −4 V and uniform subthreshold slope of 70 mV/dec. In comparison with sensors encapsulated with SiO 2 , the HfO 2 integrated nanosensors were found to improve the threshold voltage variation by 50%. Based on this work, the HfO 2 integrated SiNW demonstrates good stability for biosensing application.

Place, publisher, year, edition, pages
Elsevier B.V., 2019
Keywords
Biosensor, CMOS compatible, FEOL, HfO 2, LOC, Silicon nanowire access, Biosensors, CMOS integrated circuits, Electrodes, Fluidic devices, Hafnium oxides, Lithography, Metals, Microfluidics, MOS devices, Nanosensors, Nanowires, Oxide semiconductors, Reactive ion etching, Silica, Silicon oxides, Silicon wafers, Threshold voltage, WSI circuits, Biosensing applications, Complementary metal oxide semiconductor process, HfO2, Manufacturing process, Silicon nanowires, Threshold voltage variation, Nitrogen compounds
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-252476 (URN)10.1016/j.mee.2019.03.006 (DOI)000468708700003 ()2-s2.0-85063917094 (Scopus ID)
Note

QC 20190715

Available from: 2019-07-15 Created: 2019-07-15 Last updated: 2019-07-15Bibliographically approved
Jayakumar, G., Legallais, M., Hellström, P.-E., Mouis, M., Pignot-Paintrand, I., Stambouli, V., . . . Östling, M. (2019). Wafer-scale HfO 2 encapsulated silicon nanowire field effect transistor for efficient label-free DNA hybridization detection in dry environment. Nanotechnology, 30(18)
Open this publication in new window or tab >>Wafer-scale HfO 2 encapsulated silicon nanowire field effect transistor for efficient label-free DNA hybridization detection in dry environment
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2019 (English)In: Nanotechnology, ISSN 0957-4484, E-ISSN 1361-6528, Vol. 30, no 18Article in journal (Refereed) Published
Place, publisher, year, edition, pages
NLM (Medline), 2019
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-246421 (URN)10.1088/1361-6528/aaffa5 (DOI)30654356 (PubMedID)2-s2.0-85061994755 (Scopus ID)
Note

QC 20190329

Available from: 2019-03-29 Created: 2019-03-29 Last updated: 2019-03-29Bibliographically approved
Abedin, A., Zurauskaite, L., Asadollahi, A., Garidis, K., Jayakumar, G., Malm, B. G., . . . Östling, M. (2018). Germanium on Insulator Fabrication for Monolithic 3-D Integration. IEEE Journal of the Electron Devices Society, 6(1), 588-593
Open this publication in new window or tab >>Germanium on Insulator Fabrication for Monolithic 3-D Integration
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2018 (English)In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed) Published
Abstract [en]

A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018
Keywords
GOI, wafer bonding, selective etching, GOI MOSFET, 3D integration
National Category
Materials Chemistry
Identifiers
urn:nbn:se:kth:diva-231645 (URN)10.1109/JEDS.2018.2801335 (DOI)000435505000007 ()2-s2.0-85041650674 (Scopus ID)
Funder
Swedish Foundation for Strategic Research
Note

QC 20180904

Available from: 2018-09-04 Created: 2018-09-04 Last updated: 2018-10-19Bibliographically approved
Abedin, A., Zurauskaite, L., Asadollahi, A., Garidis, K., Jayakumar, G., Malm, B. G., . . . Östling, M. (2018). GOI fabrication for monolithic 3D integration. In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017: . Paper presented at 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Hyatt Regency San Francisco Airport Hotel Burlingame, United States, 16 October 2017 through 18 October 2017 (pp. 1-3). Institute of Electrical and Electronics Engineers (IEEE), 2018
Open this publication in new window or tab >>GOI fabrication for monolithic 3D integration
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2018 (English)In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper, Published paper (Refereed)
Abstract [en]

A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
3D Integration, GOI, GOI MOSFET, Selective Etching, Wafer Bonding
National Category
Other Engineering and Technologies
Identifiers
urn:nbn:se:kth:diva-230046 (URN)10.1109/S3S.2017.8309201 (DOI)2-s2.0-85047768082 (Scopus ID)9781538637654 (ISBN)
Conference
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Hyatt Regency San Francisco Airport Hotel Burlingame, United States, 16 October 2017 through 18 October 2017
Note

QC 20180611

Available from: 2018-06-11 Created: 2018-06-11 Last updated: 2018-06-11Bibliographically approved
Jayakumar, G., Hellström, P.-E. & Östling, M. (2018). Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application. Micromachines, 9(11), Article ID 544.
Open this publication in new window or tab >>Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application
2018 (English)In: Micromachines, ISSN 2072-666X, E-ISSN 2072-666X, Vol. 9, no 11, article id 544Article in journal (Refereed) Published
Abstract [en]

Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (V-G) and backgate voltage (V-BG). The liquid potential can be monitored using the FG. We report the transfer characteristics (I-D-V-G) of N- and P-type SiRi pixels. Further, the I-D-V-G characteristics of the SiRis are studied at different V-BG. The application of V-BG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (V-TH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large V-BG (25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large V-BG to switch ON. Thus, P-type pixels exhibit excellent I-ON/I-OFF 10(6), SS of 70-80 mV/dec and V-TH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.

Place, publisher, year, edition, pages
MDPI, 2018
Keywords
silicon ribbon pixel, silicon ribbon biosensor, lab-on-chip, SiRi CMOS integration, selective multiplexed detection, SiRi frontgate mode, SiRi backgate mode
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-240004 (URN)10.3390/mi9110544 (DOI)000451314900007 ()2-s2.0-85055740494 (Scopus ID)
Note

QC 20181210

Available from: 2018-12-10 Created: 2018-12-10 Last updated: 2018-12-10Bibliographically approved
Jayakumar, G. (2018). Silicon nanowire based devices for More than Moore Applications. (Doctoral dissertation). Stockholm, Sweden: KTH Royal Institute of Technology
Open this publication in new window or tab >>Silicon nanowire based devices for More than Moore Applications
2018 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

Silicon nanowires (SiNW) are in the spotlight for a few years in the research community as a good candidate for biosensing applications. This is attributed to their small dimensions in nanometer scale that offers high sensitivity, label-free detection and at the same time utilizing small amount of sample. While the recent research has concentrated predominantly on utilizing single or multiple SiNW for biosensing applications, very few attempts have been made to integrate SiNW with complementary-metal-oxide- semiconductor (CMOS) integration to arrive at a complete lab-on-chip (LOC) sensor. Further, the manufacturing methods reported thus far in the production of SiNW for biosensing applications have not fully exploited both the front-end-of-line (FEOL) as well as back-end-of-line (BEOL) methods in CMOS integration. Neither does the research community address CMOS integration based methods to realize multi and specific target detection that are important attributes for an ideal LOC biosensor.

Integration of SiNW with CMOS circuitry will facilitate real time detection of the output signal and in addition provide a compact small sized sensor that is fully portable operating at high speed. In order to avail the benefits of CMOS circuits and develop a large scale production friendly LOC sensor, the scheme of SiNW fabrication has to facilitate either the FEOL or BEOL CMOS integration schemes. This thesis work is focused on revealing a novel FEOL as well as BEOL scheme for integration of SiNW with CMOS circuitry. The major part of the FEOL research work is concentrated on developing a high volume SiNW manufacturing method that is suitable for industrial production. Likewise, in the BEOL scheme, predominant focus was to develop a wafer scale scheme to integrate network of nanowires (nanonets) with CMOS circuitry to manufacture a monolithic 3D above-IC LOC biosensor.

In the FEOL scheme, the SiNWs are fabricated using a revised pattern transfer technique called sidewall transfer lithography (STL). The STL method is identified as one of the efficient methods of fabricating SiNW as it uses CMOS industry grade materials that is fully compatible with the FEOL fabrication scheme. Thanks to the usage of single lithography and controlled selective etching techniques used in the STL process, the line width and aspect ratio of the SiNW can be tailored to suit the requirements for DNA hybridization detection. A fabrication process flow matching standard CMOS process integration flows has been developed to integrate SiNW with HfO2 and TiN metal gate MOSFETS. An emphasis has been placed in the design of a novel pixel matrix based SiNW LOC sensor. Specific and multi-target detection has been kept as top priority in the design of the SiNW LOC sensor. The possibility to monitor the potential of the electrolyte during the detection process using a fluid gate has been accounted in this design. Furthermore, the SiNW pixel design eliminates the intricate microfluidics and eases access to the SiNW test site using a simple photolithography mask and RIE. The SiNW and MOSFETS demonstrate excellent electrical characteristics. For the very first time, the concept to access single as well as multiple array SiNW pixels using a transistor has been successfully demonstrated.

In the BEOL scheme, the nanonets are fabricated using the bottom-up method and transferred onto a pre-fabricated CMOS wafer supplied by ams foundry. The connection between the nanonets lying above-IC and the underlying CMOS layer was established by employing a thin metal backgate electrode, backgate dielectric and metal source/drain contact pads. Many challenges in the BEOL scheme have been identified and overcome by incorporating efficient device architecture and careful selection of materials. To the first of its kind, a wafer scale process was developed to integrate nanonets with CMOS to form a monolithic 3D IC. The devices exhibit excellent electrical characteristics and lower leakage currents compared to standalone nanonet sensors fabricated on Si/SiN substrate. Further, the FEOL and BEOL integration schemes are compared and the various pro’s and con’s of both approaches for integration of SiNW with CMOS circuits to build a LOC biosensor are discussed in detail.

Finally, dry environment DNA hybridization detection is demonstrated on the surface of thin HfO2 encapsulated SiNW sensors. Upon DNA hybridization, SiNW devices exhibit threshold voltage shift larger than the noise introduced by the exposition to saline solutions used for the bio-processes. More specifically, based on a statistical analysis, it is demonstrated that 85% of the tested devices were efficient for DNA hybridization detection. The estimated density of hybridized DNA was in the order of 1010 cm-2. These promising results of realizing a SiNW based lab-on-chip platform through the FEOL and BEOL monolithic integration of SiNW and CMOS circuitry further strengthen the profile of SiNW as a nano biosensor. Indeed, this is expected to pave the way for more than Moore applications of SiNW based devices and integrated circuits.

Abstract [sv]

Kiselnanotrådar har studerats de senaste åren för biosensortillämpningar på grund av deras dimensioner i nanometer skalan som potentiellt möjliggör hög känslighet, etikettfri detektering samt en liten provmängd. Forskningen har varit fokuserad främst på användandet av enskilda eller ett flertal parallella kiselnanotrådar för biosensor tillämpningar, men lite försök har gjorts att integrera kiselnanotrådar med komplementär CMOS teknologi för att erhålla en komplett ”lab-on-chip” (LOC) sensor. Dessutom har tillverkningsmetoderna för kiselnanotrådar som hittills använts för biosensortillämpningar inte fullt utnyttjat möjligheterna som finns med integration i processflödet där transistorn tillverkas (front-end of-line, FEOL) eller i processflödet där metall ledare tillverkas för att koppla ihop transistorerna sker (back-end-of-line, BEOL). Integration av kiselnanotrådar med CMOS kretsar kommer att underlätta realtidsdetektering av sensorns utsignal och också möjliggöra en kompakt sensor som är bärbar. För att utnyttja fördelarna med CMOS kretsar och utveckla en produktionsvänlig LOC sensor så är det fördelaktigt om kiselnanotrådar kan integreras och produceras på samma chip som CMOS kretsarna. Den här avhandlingen fokuserar på nya metoder att integrera kiselnanotrådar i CMOS teknologins FEOL och BEOL processflöden. Ett huvudmål har varit att utveckla en metod att tillverka kiselnanotrådar i stor skala i FEOL med konventionell utrustning för CMOS tillverkning samt att i BEOL utveckla en process för att tillverka en biosensor med ett nätverk av kiselnanotrådar på hela kiselskivor efter metalliseringen.

I FEOL flödet har kiselnanotrådar tillverkats med en utvecklad mönsterteknik, kallad ”sidewall transfer” litografi, som utnyttjar konventionella material i CMOS tillverkning. Användandet optisk litografi och selektiva etstekniker möjligör kontroll av linjebredden hos de tillverkade kiselnanotrådarna. Ett fabrikationsflöde för att tillverka CMOS-kretsar med TiN gate elektrod och kiselnanotrådar täckta med HfO2 på samma kiselskiva har realiserats. För att möjligöra detektering av olika molekyler på samma chip så designades en pixel baserad kiselnanotråds LOC sensor där en elektrod i direkt kontakt med elektrolyten integrerades i varje pixel. Den pixelbaserad designen eliminerar intrikat mikrofluidik och elektrolyten når kiselnanotrådarna genom en öppning i oxidlagret som definieras med en fotolitografisk mask. Efter tillverkning uppvisar både kiselnanotrådarna och transistorerna excellent elektrisk karakteristik. Konceptet att adressera individuella kiselnanotrådar med hjälp av transistorer demonstreras för första gången.

I BEOL flödet så tillverkas nätverket av kiselnanotrådar med hjälp av en botten upp teknik och transfereras till tillverkade CMOS skivor från ams AG. Innan transfereringen så definierades bakgrinden med ett tunt HfO2 dielektrikum. Efter transfereringen så formerades Ni/NiSi kontakter till kiselnanotrådarna. Flera integrationsutmaningar identifierades och löste med hjälp av materialselektion och processoptimering. Komponenterna uppvisade bra elektriska karakteristik och lägre läckströmmar jämfört med referenskomponeter tillverkade med ett tjockt kiselnitrid lager som dielektrikum.

FEOL och BEOL integrationsflöden jämförs och fördelar och nackdelar diskuteras med respektive processflöde med avseende på integration av kiselnanotrådar med CMOS kretsar för att tillverka en LOC biosensor.

Detektion av DNA hybridisering demonstrerades på en sensor av kiselnanotrådar täckta med HfO2 dielektrikum. DNA hybridiseringen inducerade ett tröskelspännings-skift större än bruset från exponering i en saltlösning och 85% av de testade komponenterna detekterade DNA hybridiseringen effektivt. Densiteten av hybridiserade DNA var i storleksordningern 1010 cm-2. Dessa lovande resultat av realisering av en kiselnanotråd baserad LOC platform genom integration med CMOS kretsar visar potentialen för kiselnanotrådar som biosensorer och kan potentiellt leda till fler tillämpningar där kiselnanotrådskomponenter integreras med kretsar.

 

 

Place, publisher, year, edition, pages
Stockholm, Sweden: KTH Royal Institute of Technology, 2018. p. 259
Series
TRITA-EECS-AVL ; 2018:69
Keywords
silicon nanowire, biosensor, CMOS, sequential integration, lab-on-chip, LOC, high-K, high-K integration on SiNW biosensor, ALD, fluid gate, back gate, SiNW, SiNW pixel matrix, FEOL, pattern transfer lithography, sidewall transfer lithography, STL, multi-target bio detection, BEOL, nanonets, silicon nanonets, SiNN-FET, SiNW-FET, CMOS integration of nanowires, CMOS integration of nanonets, monolithic 3D integration of nanowires, above-IC integration of nanowires, DNA detection using SiNW, SiNW biosensor, dry environment DNA detection, DNA hybridization detection using SiNW, SiNW functionalization, SiNW silanization, SiNW grafting, FEOL integration of SiNW, BEOL integration of SiNW, sequential multiplexed biodetection, biodetection efficiency of SiNW, front end of line integration of SiNW, back end of line integration of SiNW, SiNW dry environment functionalization, APTES cross-linker, accessing SiNW test site, fluorescence microscopy of SiNW, geometry of SiNW, SiNW biosensor variability, top-down fabrication of SiNW, bottom-up fabrication of SiNW, VLS method, ams foundry CMOS process, adding functionality in BEOL process, sensor integration in BEOL process, hafnium oxide, HfO2, aluminium oxide, Al2O3, TiN backgate, Nickel source/drain, ISFET, ion sensitive field effect transistor, Overcoming Nernst limit of detection using SiNW, SiNW sub-threshold region operation, ASIC, SOC, SiGe selective epitaxy, epitaxial growth of SiNW, epitaxial growth of nanowires, epitaxial growth of nanonets, nickel silicide contacts, salicide process, high yield SiNW fabrication, high volume SiNW fabrication, silicon ribbon, SiRi pixel, SiRi biosensor, SiRi DNA detection, monolithic 3D integration of nanonets, above-IC integration of nanonets, impact of back gate voltage on silicon nanowire, impact of back gate voltage on SiNW, FDSOI, fully depleted silicon on insulator technology, metal backgate, wafer scale integration of SiNW, wafer scale integration of nanonets, impact of backgate voltage on CMOS inverter circuit, frequency divider, D flip-flop
National Category
Engineering and Technology
Research subject
Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-234918 (URN)978-91-7729-963-9 (ISBN)
Public defence
2018-10-26, Ka-Sal C (Sal Sven-Olof Öhrvik), Kistagången 16, Kista, Stockholm, 10:00 (English)
Opponent
Supervisors
Funder
EU, Horizon 2020, 688329
Note

QC 20181001

Available from: 2018-10-01 Created: 2018-09-28 Last updated: 2019-04-05Bibliographically approved
Noroozi, M., Jayakumar, G., Zahmatkesh, K., Lu, J., Hultman, L., Mensi, M., . . . Radamson, H. H. (2017). Unprecedented thermoelectric power factor in SiGe nanowires field-effect transistors. ECS Journal of Solid State Science and Technology, 6(9), Q114-Q119
Open this publication in new window or tab >>Unprecedented thermoelectric power factor in SiGe nanowires field-effect transistors
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2017 (English)In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 9, p. Q114-Q119Article in journal (Refereed) Published
Abstract [en]

In this work, a novel CMOS compatible process for Si-based materials has been presented to form SiGe nanowires (NWs) on SiGe On Insulator (SGOI) wafers with unprecedented thermoelectric (TE) power factor (PF). The TE properties of SiGe NWs were characterized in a back-gate configuration and a physical model was applied to explain the experimental data. The carrier transport in NWs was modified by biasing voltage to the gate at different temperatures. The PF of SiGe NWs was enhanced by a factor of >2 in comparison with bulk SiGe over the temperature range of 273 K to 450 K. This enhancement is mainly attributed to the energy filtering of carriers in SiGe NWs, which were introduced by imperfections and defects created during condensation process to form SiGe layer or in NWs during the processing of NWs.

Place, publisher, year, edition, pages
Electrochemical Society, 2017
National Category
Other Physics Topics
Identifiers
urn:nbn:se:kth:diva-218384 (URN)10.1149/2.0021710jss (DOI)000418363500019 ()2-s2.0-85033793013 (Scopus ID)
Funder
Swedish Foundation for Strategic Research , EM-011-0002Swedish Energy Agency, 43521-1Knut and Alice Wallenberg Foundation
Note

QC 20171128

Available from: 2017-11-28 Created: 2017-11-28 Last updated: 2018-01-08Bibliographically approved
Jayakumar, G., Legallais, M., Hellström, P.-E., Mouis, M., Stambouli, V., Ternon, C. & Östling, M. (2016). Fabrication and characterization of high-K dielectric integrated silicon nanowire sensor for DNA sensing application. In: BIOSENSING AND NANOMEDICINE IX: . Paper presented at Conference on Biosensing and Nanomedicine IX, AUG 28-31, 2016, San Diego, CA. SPIE - International Society for Optical Engineering, Article ID UNSP 99300Q.
Open this publication in new window or tab >>Fabrication and characterization of high-K dielectric integrated silicon nanowire sensor for DNA sensing application
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2016 (English)In: BIOSENSING AND NANOMEDICINE IX, SPIE - International Society for Optical Engineering, 2016, article id UNSP 99300QConference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
SPIE - International Society for Optical Engineering, 2016
Series
Proceedings of SPIE, ISSN 0277-786X ; 9930
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-200045 (URN)10.1117/12.2237350 (DOI)000389681300018 ()978-1-5106-0251-9 (ISBN)978-1-5106-0252-6 (ISBN)
Conference
Conference on Biosensing and Nanomedicine IX, AUG 28-31, 2016, San Diego, CA
Note

QC 20170126

Available from: 2017-01-26 Created: 2017-01-20 Last updated: 2017-01-26Bibliographically approved
Wang, G., Luo, J., Qin, C., Cui, H., Liu, J., Jia, K., . . . Radamson, H. H. (2016). Integration of selective epitaxial growth of SiGe/Ge layers in 14nm node FinFETs. In: ECS Transactions: . Paper presented at Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016 (pp. 273-279). Electrochemical Society Inc. (8)
Open this publication in new window or tab >>Integration of selective epitaxial growth of SiGe/Ge layers in 14nm node FinFETs
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2016 (English)In: ECS Transactions, Electrochemical Society Inc. , 2016, no 8, p. 273-279Conference paper, Published paper (Refereed)
Abstract [en]

In this study, the process integration of SiGe selective epitaxy on source/drain and SiGe/Ge bilayers selectively epitaxy on replacement Si channel regions for 14 nm node FinFETs has been presented. The epi-quality, layer profile and strain amount of the selectively grown SiGe and Ge layers were also investigated by means of various characterization tools. A series of prebaking experiments were performed for different temperatures in order to in-situ clean the Si fins prior to the SiGe S/D epitaxy. It was also found that a SiGe layer with graded Ge content was deposited as the strain relaxed buffer (SRB) layer in the channel trench prior to the Ge layer filling in the small trenches to make the void defect free.

Place, publisher, year, edition, pages
Electrochemical Society Inc., 2016
Keywords
Characterization, Epitaxial growth, Germanium, MOSFET devices, Channel region, Characterization tools, Process integration, Selective epitaxial growth, Selective epitaxy, Selectively epitaxy, Strain-relaxed buffer layers, Void defects, Silicon alloys
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-201973 (URN)10.1149/07508.0273ecst (DOI)2-s2.0-84991698876 (Scopus ID)9781607685395 (ISBN)
Conference
Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016
Note

QC 20170303

Available from: 2017-03-03 Created: 2017-03-03 Last updated: 2017-03-03Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0001-9690-2292

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