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Publications (6 of 6) Show all publications
Rosvall, K., Mohammadat, T., Ungureanu, G., Öberg, J. & Sander, I. (2018). Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors. In: : . Paper presented at 2018 21st Euromicro Conference on Digital System Design (DSD).
Open this publication in new window or tab >>Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors
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2018 (English)Conference paper, Published paper (Refereed)
Abstract [en]

System level optimization for multiple mixed-criticality applications on shared networked multiprocessor platforms is extremely challenging. Substantial complexity arises from the interdependence between the multiple subproblems of mapping, scheduling and platform configuration under the consideration of several, potentially orthogonal, performance metrics and constraints. Instead of using heuristic algorithms and problem decomposition, novel unified design space exploration (DSE) approaches based on Constraint Programming (CP) have in the recent years shown promising results. The work in this paper takes advantage of the modularity of CP models, in order to support heterogeneous multiprocessor Network-on-Chip (NoC) with Temporally Disjoint Networks (TDNs) aware message injection. The DSE supports a range of design criteria, in particular the optimization and satisfaction of power and throughput. In addition, the DSE now provides a valid configuration for the TDNs that guarantees the performance required to fulfil the design goals. The experiments show the capability of the approach to find low-power and high-throughput designs, and validate a resulting design on a physical TDN-based NoC implementation.

National Category
Engineering and Technology Electrical Engineering, Electronic Engineering, Information Engineering Embedded Systems Computer Systems
Identifiers
urn:nbn:se:kth:diva-239007 (URN)10.1109/DSD.2018.00011 (DOI)2-s2.0-85056465815 (Scopus ID)978-1-5386-7377-5 (ISBN)
Conference
2018 21st Euromicro Conference on Digital System Design (DSD)
Note

QC 20181114

Available from: 2018-11-14 Created: 2018-11-14 Last updated: 2019-03-20Bibliographically approved
Rosvall, K. & Sander, I. (2018). Flexible and Tradeoff-Aware Constraint-Based Design Space Exploration for Streaming Applications on Heterogeneous Platforms. ACM Transactions on Design Automation of Electronic Systems, 23(2), Article ID 21.
Open this publication in new window or tab >>Flexible and Tradeoff-Aware Constraint-Based Design Space Exploration for Streaming Applications on Heterogeneous Platforms
2018 (English)In: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, E-ISSN 1557-7309, Vol. 23, no 2, article id 21Article in journal (Refereed) Published
Abstract [en]

Due to its complexity, the problem of mapping and scheduling streaming applications on heterogeneous MPSoCs under real-time and performance constraints has traditionally been tackled by incomplete heuristic algorithms. In recent years, approaches based on Constraint Programming (CP) have shown promising results as complete methods for finding optimal mappings, in particular concerning throughput. However, so far none of the available CP approaches consider the tradeoff between throughput and buffer requirements or throughput and power consumption. This article integrates tradeoff awareness into the CP model and introduces a two-step solving approach that utilizes the advantages of heuristics, while still keeping the completeness property of CP. With a number of experiments considering several streaming applications and different platform models, the article illustrates not only the efficiency of the presented model but also its suitability for solving different problems with various combinations of performance constraints.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2018
Keywords
Constraint programming, correct-by-construction, design space exploration, performance analysis
National Category
Control Engineering
Identifiers
urn:nbn:se:kth:diva-222443 (URN)10.1145/3133210 (DOI)000423468900009 ()
Note

QC 20180219

Available from: 2018-02-19 Created: 2018-02-19 Last updated: 2018-05-24Bibliographically approved
Khalilzad, N., Rosvall, K. & Sander, I. (2017). A modular design space exploration framework for multiprocessor real-time systems. In: Forum on Specification and Design Languages: . Paper presented at 2016 Forum on Specification and Design Languages, FDL 2016, 14 September 2016 through 16 September 2016. IEEE, Article ID 7880377.
Open this publication in new window or tab >>A modular design space exploration framework for multiprocessor real-time systems
2017 (English)In: Forum on Specification and Design Languages, IEEE, 2017, article id 7880377Conference paper, Published paper (Refereed)
Abstract [en]

Embedded system designers often face a large number of design alternatives when designing complex systems. A designer must select an alternative which satisfies application constraints (e.g. timing requirements) while optimizing system level objectives such as overall energy consumption. The size of design space is often very large giving rise to the need for systematic Design Space Exploration (DSE) methods. In this paper we address the DSE problem for real-time applications that belong to two different domains: (i) streaming applications modeled using the synchronous dataflow graphs; (ii) feedback control tasks modeled using the periodic task model. We consider a heterogeneous multiprocessor platform in which processors communicate through a predictable bus architecture. We present our DSE tool in which the DSE problem is modeled as a constraint satisfaction problem, and it is solved using a constraint programming solver. This approach provides a modular framework in which different constraints such as deadline, throughput and energy consumption can easily be plugged depending on the system being designed.

Place, publisher, year, edition, pages
IEEE, 2017
Keywords
Constraint Programming, Design Space Exploration, Multiprocessors, Periodic Tasks, Real-Time Systems, Synchronous Dataflow, Computer programming, Constraint satisfaction problems, Constraint theory, Data flow analysis, Embedded systems, Energy utilization, Interactive computer systems, Multiprocessing systems, Specifications, Real time systems
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-210144 (URN)10.1109/FDL.2016.7880377 (DOI)2-s2.0-85017111938 (Scopus ID)9791092279177 (ISBN)
Conference
2016 Forum on Specification and Design Languages, FDL 2016, 14 September 2016 through 16 September 2016
Note

QC 20170630

Available from: 2017-06-30 Created: 2017-06-30 Last updated: 2017-06-30Bibliographically approved
Grüttner, K., Görgen, R., Schreiner, S., Herrera, F., Peñil, P., Medina, J., . . . Quaglia, D. (2017). CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties. Microprocessors and microsystems, 51, 39-55
Open this publication in new window or tab >>CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties
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2017 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 51, p. 39-55Article in journal (Refereed) Published
Abstract [en]

The increasing processing power of today's HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels. This article presents an overview of the CONTREX European project, its main innovative technology (extension of a model based design approach, functional and extra-functional analysis with executable models and run-time management) and the final results of three industrial use-cases from different domain (avionics, automotive and telecommunication).

Place, publisher, year, edition, pages
Elsevier B.V., 2017
Keywords
Criticality (nuclear fission), Energy efficiency, Project management, Computing resource, Extra-functional properties, Industrial use case, Innovative technology, Mixed criticalities, Model-based design approaches, Segregation mechanism, Timing constraints, Embedded systems
National Category
Computer Sciences
Identifiers
urn:nbn:se:kth:diva-216480 (URN)10.1016/j.micpro.2017.03.012 (DOI)000404710100004 ()2-s2.0-85018492812 (Scopus ID)
Note

QC 20171201

Available from: 2017-12-01 Created: 2017-12-01 Last updated: 2018-01-13Bibliographically approved
Rosvall, K. & Sander, I. (2014). A constraint-based design space exploration framework for real-time applications on MPSoCs. In: Proceedings -Design, Automation and Test in Europe, DATE 2014: . Paper presented at 17th Design, Automation and Test in Europe, DATE 2014, Dresden, Germany, 24 March 2014 through 28 March 2014 (pp. 1-6). IEEE Computer Society
Open this publication in new window or tab >>A constraint-based design space exploration framework for real-time applications on MPSoCs
2014 (English)In: Proceedings -Design, Automation and Test in Europe, DATE 2014, IEEE Computer Society, 2014, p. 1-6Conference paper, Published paper (Refereed)
Abstract [en]

Design space exploration (DSE) is a critical step in the design process of real-time multiprocessor systems. Combining a formal base in form of SDF graphs with predictable platforms providing guaranteed QoS, the paper proposes a flexible and extendable DSE framework that can provide performance guarantees for multiple applications implemented on a shared platform. The DSE framework is formulated in a declarative style as interprocess communication-aware constraint programming (CP) model. Apart from mapping and scheduling of application graphs, the model supports design constraints on several cost and performance metrics, as e.g. memory consumption and achievable throughput. Using constraints with different compliance level, the framework introduces support for mixed criticality in the CP model. The potential of the approach is demonstrated by means of experiments using a Sobel filter, a SUSAN filter, a RASTA-PLP application and a JPEG encoder.

Place, publisher, year, edition, pages
IEEE Computer Society, 2014
Series
Design, Automation, and Test in Europe Conference and Exhibition. Proceedings, ISSN 1530-1591
Keywords
Computer programming, Constraint theory, Scheduling, System-on-chip, Achievable throughputs, Constraint programming, Constraint-based design, Design space exploration, Multi processor systems, Multiple applications, Performance guarantees, Real-time application
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-160515 (URN)10.7873/DATE.2014.339 (DOI)000354965500326 ()2-s2.0-84903826264 (Scopus ID)978-398153702-4 (ISBN)
Conference
17th Design, Automation and Test in Europe, DATE 2014, Dresden, Germany, 24 March 2014 through 28 March 2014
Note

QC 20150224

Available from: 2015-02-24 Created: 2015-02-23 Last updated: 2015-08-18Bibliographically approved
Li, S., Farahini, N., Hemani, A., Rosvall, K. & Sander, I. (2013). System level synthesis of hardware for DSP applications using pre-characterized function implementations. In: 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS): . Paper presented at 11th ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013; Montreal, QC; Canada; 29 September 2013 through 4 October 2013. IEEE
Open this publication in new window or tab >>System level synthesis of hardware for DSP applications using pre-characterized function implementations
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2013 (English)In: 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), IEEE , 2013Conference paper, Published paper (Refereed)
Abstract [en]

SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. SYLVA synthesizes in terms of pre-characterized function implementations (FTMPs). It explores the design space in three dimensions, number of FTMPs, type of FTMPs and pipeline parallelism between the producing and consuming FTMPs. We introduce timing and interface model of FTMPs to enable reuse and automatic generation of Global Interconnect and Control (GLIC) to glue the FTMPs together into a working system. SYLVA has been evaluated by applying it to five realistic DSP applications and results analyzed for design space exploration, efficacy in generating GLIC by comparing to manually generated GLIC and accuracy of design space exploration by comparing the area and energy costs considered during the design space exploration based on pre-characterized FIMPs and the final results.

Place, publisher, year, edition, pages
IEEE, 2013
Keywords
Design space exploration, Electronic system level synthesis, Reuse, Synchronous data flow, System level synthesis
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-143296 (URN)10.1109/CODES-ISSS.2013.6659003 (DOI)2-s2.0-84892642437 (Scopus ID)978-147991417-3 (ISBN)
Conference
11th ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013; Montreal, QC; Canada; 29 September 2013 through 4 October 2013
Note

QC 20140319

Available from: 2014-03-19 Created: 2014-03-19 Last updated: 2014-03-19Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0001-9350-7772

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