A wide range of Internet of Things devices, platforms and applications have been implemented in the past decade. The variation in platforms, communication protocols and data formats of these systems creates islands of applications. Many organizations are working towards standardizing the technologies used at different layers of communication in these systems. However, interoperability still remains one of the main challenges towards realizing the grand vision of IoT. Intergration approaches proven in the existing Internet or enterprise applications are not suitable for the IoT, mainly due to the nature of the devices involved; the majority of the devices are resource constrained. To address this problem of interoperability, our work considers various types of IoT application domains, architecture of the IoT and the works of standards organizations to give a holistic abstract model of IoT. According to this model, there are three computing layers, each with a different level of interoperability needs — technical, syntactic or semantic. This work presents a Web of Virtual Things (WoVT) server that can be deployed at the middle layer of IoT (Fog layer) and Cloud to address the problem of interoperability. It exposes a REST like uniform interface for syntactic integration of devices at the bottom layer of IoT (perception layer). An additional RESTful api is used for integration with other similar WoVT servers at the Fog or the Cloud layer. The server uses a state of the art architecture to enable this integration pattern and provides means towards semantic interoperability. The analysis and evaluation of the implementation, such as performance, resource utilization and security perspectives, are presented. The simulation results demonstrate that an integrated and scalable IoT through the web of virtual things can be realized.

It remains a challenge to run Deep Learning in devices with stringent power budget in the Internet-of-Things. This paper presents a low-power accelerator for processing Convolutional Neural Networks on the embedded devices. The power reduction is realized by exploring data reuse in three different aspects, with regards to convolution, filter and input features. A systolic-like data flow is proposed and applied to rows of Processing Elements (PEs), which facilitate reusing the data during convolution. Reuse of input features and filters is achieved by arranging the PE array in a 3D tiled architecture, whose dimension is 3 x 14 x 4. Local storage within PEs is therefore reduced and only cost 17.75 kB, which is 20% of the state-of-the-art. With dedicated delay chains in each PE, this accelerator is reconfigurable to suit various parameter settings of convolutional layers. Evaluated in UMC 65 nm low leakage process, the accelerator can reach a peak performance of 84 GOPS and consume only 136 mW at 250 Mhz.

A compact, robust, chipless radio frequency identification (RFID) tag is proposed. Resonant elements patterned in a concentric fashion encode data in the spectral domain employing frequency shift encoding. The proposed tag encodes 28.25 data bits over a miniscule physical footprint of 25 x 25 mm(2). The formulated scheme is demonstrated to be viable for encoding of temporal variables. The electromagnetic performance of the presented design is investigated for different laminates: Rogers RT/duroid (R) 5880 and Taconic TLX-0. Multiple tag prototypes employing a variety of substrates are realized and evaluated for in-laboratory performance. The proposed design is compared with existing work reported in literature. Code density of 4.52 bits/cm(2) has been successfully achieved. The tag design operates from 3.07 to 10.6 GHz and is readily realizable on flexible laminates. Smart retail, intelligent packaging, adaptive ticketing, and similar time-related applications can be materialized using the proposed tag.

This work presents a compact, quad-band planar antenna intended for assimilation into flexible and conformal devices. The CPW-fed semicircular shaped prototype with rake-shaped slots is designed, realized and characterized experimentally. The frequency bands covered by the proposed radiator are centered at 2.5, 3.7, 5.5 and 8 GHz with measured impedance bandwidths of 16%, 13.5%, 11.8% and 14.63%, respectively. The proposed antenna is thus enabled to support WLAN, ISM, Bluetooth, WiMAX LTE and X-band applications. The antenna exhibits a significant gain. The radiation characteristics of the proposed radiator are measured in concave and convex bent shapes at various radii to analyze its flexibility. Performance of the antenna remains almost unaffected in the bent situation. Measurements demonstrate good coherence with simulations. The compactness and good performance of the design both in bent and unbent conditions proves it to be the better contender for future multiband conformal wireless applications.

In the knowledge-based society, the legacy education system does not provide the needed skills for creative engineers especially enhancing student innovation and entrepreneurship capacity. Triple-helix model is a concept that aims to bond universities, industry and government in a bid to create innovations. In Europe, integrating research, education, and innovation together in a comprehensive manner has been the major driving force for local and European university development, as example in the form of European Institute Innovation Technology (EIT). At KTH, there are activities that alien the Teaching and Learning Activities (TLA) with different task group with the aim of creating a mutual innovation capacity to contribute solutions for major social challenges. Some of these task groups are Cross-Cultural Faculty Development for Challenge Driven Education, Global learning and digital platform and open innovation platform for learning. The progress and the success are measured by the number of joint student teams and their skills, knowledge development with the follow-up workshop, and the ongoing research and results of the socio-oriented projects. To enhance TLA and the teaching and learning practices, we have developed new curriculums (MSc. and PhD) for our partners to spark innovation and entrepreneurship where the students interact with Open Lab activities. The assessments show that the enrolled students have gained creative skills in dealing with engineering problem and consolidate their knowledge to improve the future TLA and the Intended Learning Outcome (ILO).

This article expounds a multi-band compact shaped antenna, which is based on CPW ground plane. FR-4 with a thickness of 1.6 mm is used as a substrate for the proposed antenna. The proposed antenna is capable of operating at 1.56 GHz for (Global Positioning System), 2.45 GHz (Wireless Local Area Network) and 4.49 GHz (Aeronautical Mobile Telemetry (AMT) fixed services). The efficiency at 1.56, 2.45, and 4.49 GHz is 79.7, 76.9 and 76.7%, respectively. The VSWR of the presented antenna is less than 1.5 at all the desired resonance modes, which confirms its good impedance matching. The performance of the proposed antenna is evaluated in terms of VSWR, return loss, radiation pattern and efficiency. CST (R) MWS (R) software is used for simulations. In order to validate the simulation results, a prototype of the designed antenna is fabricated and a good agreement is found between the simulated and measured results.

A compact 27-bit linearly polarized chipless radio frequency identification tag is presented in this research. The proposed tag is designed with an overall tag dimension of 23 x 23 mm(2). The tag comprises of metallic (copper) rings-based structure loaded with slots. These slots correspond to a particular sequence of bits. The circular tag is analysed using 2 different substrates, that is, Rogers RT/duroid/5870 and flexible Rogers RT/duroid/5880. The radar cross-section response of frequency signatured tag is analysed for humidity and temperature sensor designs. Humidity sensing is achieved by deploying a DuPont Kapton HN heat resistant sheet on the shortest slot of the tag, that is, the sensing slot. Temperature sensing is attained using Rogers RT/duroid/5870 and Stanyl polyamide as a combined substrate. Hence, the miniaturized, robust, and flexible tag can be deployed over irregular surfaces for sensing purposes.

A compact chipless RFID tag with robust readable features is presented in this paper. The tag is made up of novel concentric butterfly slot resonators. Bit data is encoded in the frequency signature of the tag. Each slot corresponds to a resonance peak representing a bit '1', whereas an absence of the peak signifies a bit '0'. Proposed resonator design demonstrates insensitivity to different polarization and incident angles of the linearly polarized impinging electromagnetic wave. The tag operates in the frequency band of 4.7-9.7 GHz, limited within the license free ultra wide-band. Rogers RT/duroid (R) 5880 substrate is used to realize a 10-bit capacity design that spans 14 x 14 mm(2) resulting in a bit density of 5.1 bits/cm(2).

A client-server architecture style is one of the common approaches enabling separation of concerns in distributed systems. In the Internet of Things architecture, this approach exists in different configuration of sensors, actuators, gateways in the Fog layer and servers in the Cloud. This configuration affects the degree of interoperability, scalability and other functional and non-functional system requirements. In this paper, we reflect on best practices in the web and REST style to address IoT challenges; one of the constraints in REST, Code on Demand, is used for IoT to enhance the flexibility and interoperability of resource constrained clients at the perception layer. Scripts written in a domain specific language, DoS-IL, are organized and stored at the Fog layer for sensor and actuators nodes to request and execute the incoming script. A generic application layer protocol and RESTful server are presented along with experimental results.

This work presents an algorithm to select a low-cost modulus for the implementation of Blum Blum Shub pseudorandom number generator in an FPGA device. Additionally, it elaborates a low-latency architecture for the BBS algorithm suitable for the security service of the IEEE 1609.2 standard. The architecture uses diminished-1 arithmetic and is log2($N$) faster than previously reported implementation using Montgomery multiplier. The architecture is able to implement 224-bit and 256-bit BBS sequences. Synthesis results show that the latencies for the 224-bit and 256-bit BBS are, respectively, 1.12μs and 1.28μs.