An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part has 256 ( $16\times 16$ ) pixels. The digital circuit part for row and column selection contains two 4-to-16 decoders and one 8-bit counter. The digital circuits are designed in transistor-transistor logic (TTL). The entire circuit has 1959 transistors. It is the first demonstration of SiC opto-electronic on-chip integration. The function of the image sensor up to 400 degrees C has been verified by taking photos of the spatial patterns masked from UV light. The image sensor would play a significant role in UV photography, which has important applications in astronomy, clinics, combustion detection and art.

Low-parasitic-capacitance 4H-SiC pMOSFETs were demonstrated for high-frequency CMOS inverters. In these pMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain capacitance) were investigated and low parasitic capacitance was achieved by the trench gate structure.

This letter presents the design, fabrication, and characterization of a 4H-SiC n-p-n bipolar junction transistor as a switch controlling an on-chip integrated p-i-n photodiode. The transistor and photodiode share the same epitaxial layers and topside contacts for each terminal. By connecting the collector of the transistor and the anode of the photodiode, the photo current from the photodiode is switched off at low base voltage (cutoff region of the transistor) and switched on at high base voltage (saturation region of the transistor). The transfer voltage of the circuit decreases as the ambient temperature increases (2 mV/degrees C). Both the on-state and off-state current of the circuit have a positive temperature coefficient and the on/off ratio is >80 at temperature ranged from 25 degrees C to 400 degrees C. It is proposed that the on/off ratio can be increased by similar to 1000 times by adding a light blocking layer on the transistor to reduce light induced off-state current in the circuit.

This correspondence highlights an error in the above-titled paper. The corrected material is presented here.

The advance of miniaturized and low-power electronics has a striking impact on the development of energy storage devices with constantly tougher constraints in terms of form factor and performance. Microsupercapacitors (MSCs) are considered a potential solution to this problem, thanks to their compact device structure. Great efforts have been made to maximize their performance with new materials like graphene and to minimize their production cost with scalable fabrication processes. In this regard, we developed a full inkjet printing process for the production of all-graphene microsupercapacitors with electrodes based on electrochemically exfoliated graphene and an ultrathin solid-state electrolyte based on nano-graphene oxide. The devices exploit the high ionic conductivity of nano-graphene oxide coupled with the high electrical conductivity of graphene films, yielding areal capacitances of up to 313 mu F cm-2 at 5 mV s-1 and high power densities of up to 4 mW cm-3 with an overall device thickness of only 1 mu m.

Nanoelectromechanical system (NEMS) sensors and actuators could be of use in the development of next-generation mobile, wearable and implantable devices. However, these NEMS devices require transducers that are ultra-small, sensitive and can be fabricated at low cost. Here, we show that suspended double-layer graphene ribbons with attached silicon proof masses can be used as combined spring–mass and piezoresistive transducers. The transducers, which are created using processes that are compatible with large-scale semiconductor manufacturing technologies, can yield NEMS accelerometers that occupy at least two orders of magnitude smaller die area than conventional state-of-the-art silicon accelerometers. With our devices, we also extract the Young’s modulus values of double-layer graphene and show that the graphene ribbons have significant built-in stresses.

Silicon nanowires (SiNWs) are a widely used technology for sensing applications. Complementary metal-oxide-semiconductor (CMOS) integration of SiNWs advances lab-on-chip (LOC) technology and offers opportunities for read-out circuit integration, selective and multiplexed detection. In this work, we propose novel scalable pixel-based biosensors exploiting the integration of SiNWs with CMOS in fully-depleted silicon-on-insulator technology. A detailed description of the wafer-scale fabrication of SiNW pixels using the CMOS compatible sidewall-transfer-lithography as an alternative to widely investigated time inefficient e-beam lithography is presented. Each 60 nm wide SiNWs sensor is monolithically connected to a control transistor and novel on-chip fluid-gate forming an individual pixel that can be operated in two modes: biasing transistor frontgate (V-G) or substrate backgate (V-BG). We also present the first electrical results of single N and P-type SiNW pixels. In frontgate mode, N and P-type SiNW pixels exhibit subthreshold slope (SS) approximate to 70-80 mV/dec and I-on/I-off approximate to 10(5). The N-type and P-type pixels have an average threshold voltage, Vth of -1.7 V and 0.85 V respectively. In the backgate mode, N and P-type SiNW pixels exhibit SS approximate to 100-150 mV/dec and I-on/I-off approximate to 10(6). The N and P-type pixels have an average V-th of 5 V and -2.5 V respectively. Further, the influence of the backgate and frontgate voltage on the switching characteristics of the SiNW pixels is also studied. In the frontgate mode, the Vth of the SiNW pixels can be tuned at 0.2 V for 1 V change in V-BG for N-type or at -0.2 V for -1 V change in V-BG for P-type pixels. In the backgate mode, it is found that for stable operation of the pixels, the V-G of the N and P-type transistors must be in the range 0.5-2.5 V and 0 V to -2.5 V respectively.

Submicron 4H-SiC MOSFETs are attractive for high frequency operation of 4H-SiC integrated circuits. However, the short channel effects, such as threshold voltage lowering, would be induced at the short-channel devices. In this work, short channel effects were investigated with planar and trench 4H-SiC MOSFETs, and the suppression of the short channel effect with the trench structure was achieved.