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Publications (10 of 40) Show all publications
Hou, S., Hellström, P.-E., Zetterling, C.-M. & Östling, M. (2019). A 4H-SiC BJT as a Switch for On-Chip Integrated UV Photodiode. IEEE Electron Device Letters, 40(1), 51-54
Open this publication in new window or tab >>A 4H-SiC BJT as a Switch for On-Chip Integrated UV Photodiode
2019 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 40, no 1, p. 51-54Article in journal (Refereed) Published
Abstract [en]

This letter presents the design, fabrication, and characterization of a 4H-SiC n-p-n bipolar junction transistor as a switch controlling an on-chip integrated p-i-n photodiode. The transistor and photodiode share the same epitaxial layers and topside contacts for each terminal. By connecting the collector of the transistor and the anode of the photodiode, the photo current from the photodiode is switched off at low base voltage (cutoff region of the transistor) and switched on at high base voltage (saturation region of the transistor). The transfer voltage of the circuit decreases as the ambient temperature increases (2 mV/degrees C). Both the on-state and off-state current of the circuit have a positive temperature coefficient and the on/off ratio is >80 at temperature ranged from 25 degrees C to 400 degrees C. It is proposed that the on/off ratio can be increased by similar to 1000 times by adding a light blocking layer on the transistor to reduce light induced off-state current in the circuit.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2019
Keywords
4H-SiC, BJT, UV, photodiode, high temperature, switch
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-242990 (URN)10.1109/LED.2018.2883749 (DOI)000456172600013 ()2-s2.0-85057777289 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation
Note

QC 20190204

Available from: 2019-02-04 Created: 2019-02-04 Last updated: 2019-04-10Bibliographically approved
Östling, M. (2019). Editorial Exciting Progress. IEEE Journal of the Electron Devices Society, 7, Article ID 8656607.
Open this publication in new window or tab >>Editorial Exciting Progress
2019 (English)In: IEEE Journal of the Electron Devices Society, Vol. 7, article id 8656607Article in journal (Refereed) Published
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2019
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-252117 (URN)10.1109/JEDS.2019.2898562 (DOI)2-s2.0-85062697066 (Scopus ID)
Note

QC 20190523

Available from: 2019-05-23 Created: 2019-05-23 Last updated: 2019-05-23Bibliographically approved
Delekta, S. S., Adolfsson, K. H., Benyahia Erdal, N., Hakkarainen, M., Östling, M. & Li, J. (2019). Fully inkjet printed ultrathin microsupercapacitors based on graphene electrodes and a nano-graphene oxide electrolyte. Nanoscale, 11(21), 10172-10177
Open this publication in new window or tab >>Fully inkjet printed ultrathin microsupercapacitors based on graphene electrodes and a nano-graphene oxide electrolyte
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2019 (English)In: Nanoscale, ISSN 2040-3364, E-ISSN 2040-3372, Vol. 11, no 21, p. 10172-10177Article in journal (Refereed) Published
Abstract [en]

The advance of miniaturized and low-power electronics has a striking impact on the development of energy storage devices with constantly tougher constraints in terms of form factor and performance. Microsupercapacitors (MSCs) are considered a potential solution to this problem, thanks to their compact device structure. Great efforts have been made to maximize their performance with new materials like graphene and to minimize their production cost with scalable fabrication processes. In this regard, we developed a full inkjet printing process for the production of all-graphene microsupercapacitors with electrodes based on electrochemically exfoliated graphene and an ultrathin solid-state electrolyte based on nano-graphene oxide. The devices exploit the high ionic conductivity of nano-graphene oxide coupled with the high electrical conductivity of graphene films, yielding areal capacitances of up to 313 mu F cm-2 at 5 mV s-1 and high power densities of up to 4 mW cm-3 with an overall device thickness of only 1 mu m.

Place, publisher, year, edition, pages
Royal Society of Chemistry, 2019
National Category
Chemical Sciences
Identifiers
urn:nbn:se:kth:diva-254076 (URN)10.1039/c9nr01427f (DOI)000470697800002 ()31107494 (PubMedID)2-s2.0-85066626832 (Scopus ID)
Note

QC 20190624

Available from: 2019-06-24 Created: 2019-06-24 Last updated: 2019-08-16Bibliographically approved
Jayakumar, G. & Östling, M. (2019). Pixel-based biosensor for enhanced control: silicon nanowires monolithically integrated with field-effect transistors in fully depleted silicon on insulator technology. Nanotechnology, 30(22), Article ID 225502.
Open this publication in new window or tab >>Pixel-based biosensor for enhanced control: silicon nanowires monolithically integrated with field-effect transistors in fully depleted silicon on insulator technology
2019 (English)In: Nanotechnology, ISSN 0957-4484, E-ISSN 1361-6528, Vol. 30, no 22, article id 225502Article in journal (Refereed) Published
Abstract [en]

Silicon nanowires (SiNWs) are a widely used technology for sensing applications. Complementary metal-oxide-semiconductor (CMOS) integration of SiNWs advances lab-on-chip (LOC) technology and offers opportunities for read-out circuit integration, selective and multiplexed detection. In this work, we propose novel scalable pixel-based biosensors exploiting the integration of SiNWs with CMOS in fully-depleted silicon-on-insulator technology. A detailed description of the wafer-scale fabrication of SiNW pixels using the CMOS compatible sidewall-transfer-lithography as an alternative to widely investigated time inefficient e-beam lithography is presented. Each 60 nm wide SiNWs sensor is monolithically connected to a control transistor and novel on-chip fluid-gate forming an individual pixel that can be operated in two modes: biasing transistor frontgate (V-G) or substrate backgate (V-BG). We also present the first electrical results of single N and P-type SiNW pixels. In frontgate mode, N and P-type SiNW pixels exhibit subthreshold slope (SS) approximate to 70-80 mV/dec and I-on/I-off approximate to 10(5). The N-type and P-type pixels have an average threshold voltage, Vth of -1.7 V and 0.85 V respectively. In the backgate mode, N and P-type SiNW pixels exhibit SS approximate to 100-150 mV/dec and I-on/I-off approximate to 10(6). The N and P-type pixels have an average V-th of 5 V and -2.5 V respectively. Further, the influence of the backgate and frontgate voltage on the switching characteristics of the SiNW pixels is also studied. In the frontgate mode, the Vth of the SiNW pixels can be tuned at 0.2 V for 1 V change in V-BG for N-type or at -0.2 V for -1 V change in V-BG for P-type pixels. In the backgate mode, it is found that for stable operation of the pixels, the V-G of the N and P-type transistors must be in the range 0.5-2.5 V and 0 V to -2.5 V respectively.

Place, publisher, year, edition, pages
IOP PUBLISHING LTD, 2019
Keywords
silicon nanowire pixel; silicon nanowire biosensor; lab-on-chip; SiNW CMOS integration; selective multiplexed detection; SiNW frontgate mode; SiNW backgate mode
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-248056 (URN)10.1088/1361-6528/ab0469 (DOI)000461650400002 ()30721898 (PubMedID)2-s2.0-85063252229 (Scopus ID)
Note

QC 20190429

Available from: 2019-04-29 Created: 2019-04-29 Last updated: 2019-04-29Bibliographically approved
Hou, S., Shakir, M., Hellström, P.-E., Zetterling, C.-M. & Östling, M. (2019). Process Control and Optimization of 4H-SiC Semiconductor Devices and Circuits. In: Proceedings of the 3rd Electron Devices Technology and Manufacturing, (EDTM) Conference 2019: . Paper presented at The 3rd Electron Devices Technology and Manufacturing (EDTM) Conference. IEEE
Open this publication in new window or tab >>Process Control and Optimization of 4H-SiC Semiconductor Devices and Circuits
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2019 (English)In: Proceedings of the 3rd Electron Devices Technology and Manufacturing, (EDTM) Conference 2019, IEEE, 2019Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
IEEE, 2019
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-248421 (URN)
Conference
The 3rd Electron Devices Technology and Manufacturing (EDTM) Conference
Note

QC 20190411

Available from: 2019-04-08 Created: 2019-04-08 Last updated: 2019-04-11Bibliographically approved
Shakir, M., Hou, S., Hedayati, R., Malm, B. G., Östling, M. & Zetterling, C.-M. (2019). Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications. Electronics, 8(5)
Open this publication in new window or tab >>Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications
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2019 (English)In: Electronics, ISSN 2079-9292,, Vol. 8, no 5Article in journal (Other academic) Published
Abstract [en]

A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta (β) and collector current (IC) variation of SiC devices as temperature increases. The PDK-based complex digital ICsdesign flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.

Keywords
Process Design Kit (PDK); bipolar logic gates; high temperature digital integrated circuits (ICs); transistor–transistor logic (TTL); SiC bipolar transistor; SiC VLSI Circuits
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-248424 (URN)10.3390/electronics8050496 (DOI)
Funder
Knut and Alice Wallenberg Foundation, Working on Venus
Note

QC 20190410

Available from: 2019-04-08 Created: 2019-04-08 Last updated: 2019-05-23Bibliographically approved
Jayakumar, G., Hellström, P.-E. & Östling, M. (2019). Utilizing the superior etch stop quality of HfO 2 in the front end of line wafer scale integration of silicon nanowire biosensors. Microelectronic Engineering, 212, 13-20
Open this publication in new window or tab >>Utilizing the superior etch stop quality of HfO 2 in the front end of line wafer scale integration of silicon nanowire biosensors
2019 (English)In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 212, p. 13-20Article in journal (Refereed) Published
Abstract [en]

Silicon nanowire (SiNW) biosensors have received a special attention from the research community due to its ability to detect a range of species. The nano feature size of the SiNW has been exploited to fabricate small, low-cost, robust, portable, real-time read-out biosensors. These sensors are manufactured by two methods – top-down or bottom-up. Instead of the bottom-up method, the top-down approach is widely used due to its compatibility with complementary metal-oxide semiconductor (CMOS) process and scope of mass production. However, in the top-down method, the post fabrication microfluidic channel integration to access the SiNW test site remains complex and challenging. Since the nanosensor is expected to operate in a bio environment, it is essential to passivate the metal electrodes while pathways have to be made to access the test site. In this paper, we present a relatively easier method to access the SiNW test site without employing complex microfluidic channels while achieving leakage free passivation of metal electrodes and preserving the integrity of the nanosensor. This is accomplished in the last step of the manufacturing process by employing a lithography mask and reactive ion etching (RIE). HfO 2 integrated crystalline silicon nanosensors are manufactured using novel top-down front end of line (FEOL) sidewall transfer lithography (STL) process. HfO 2 acts as an etch stop layer while performing RIE in the last step to access the sensor test site. The 100 mm wafer scale results of 20 nm × 60 nm × 6 μm (H x W x L) p-type nanosensors shows an average I on /I off ≥ 10 5 with maximum turn-on voltage of −4 V and uniform subthreshold slope of 70 mV/dec. In comparison with sensors encapsulated with SiO 2 , the HfO 2 integrated nanosensors were found to improve the threshold voltage variation by 50%. Based on this work, the HfO 2 integrated SiNW demonstrates good stability for biosensing application.

Place, publisher, year, edition, pages
Elsevier B.V., 2019
Keywords
Biosensor, CMOS compatible, FEOL, HfO 2, LOC, Silicon nanowire access, Biosensors, CMOS integrated circuits, Electrodes, Fluidic devices, Hafnium oxides, Lithography, Metals, Microfluidics, MOS devices, Nanosensors, Nanowires, Oxide semiconductors, Reactive ion etching, Silica, Silicon oxides, Silicon wafers, Threshold voltage, WSI circuits, Biosensing applications, Complementary metal oxide semiconductor process, HfO2, Manufacturing process, Silicon nanowires, Threshold voltage variation, Nitrogen compounds
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-252476 (URN)10.1016/j.mee.2019.03.006 (DOI)000468708700003 ()2-s2.0-85063917094 (Scopus ID)
Note

QC 20190715

Available from: 2019-07-15 Created: 2019-07-15 Last updated: 2019-07-15Bibliographically approved
Jayakumar, G., Legallais, M., Hellström, P.-E., Mouis, M., Pignot-Paintrand, I., Stambouli, V., . . . Östling, M. (2019). Wafer-scale HfO 2 encapsulated silicon nanowire field effect transistor for efficient label-free DNA hybridization detection in dry environment. Nanotechnology, 30(18)
Open this publication in new window or tab >>Wafer-scale HfO 2 encapsulated silicon nanowire field effect transistor for efficient label-free DNA hybridization detection in dry environment
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2019 (English)In: Nanotechnology, ISSN 0957-4484, E-ISSN 1361-6528, Vol. 30, no 18Article in journal (Refereed) Published
Place, publisher, year, edition, pages
NLM (Medline), 2019
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-246421 (URN)10.1088/1361-6528/aaffa5 (DOI)30654356 (PubMedID)2-s2.0-85061994755 (Scopus ID)
Note

QC 20190329

Available from: 2019-03-29 Created: 2019-03-29 Last updated: 2019-03-29Bibliographically approved
Delekta, S. S., Östling, M. & Li, J. (2019). Wet Transfer of Inkjet Printed Graphene for Microsupercapacitors on Arbitrary Substrates. ACS Applied Energy Materials, 2(1), 158-163
Open this publication in new window or tab >>Wet Transfer of Inkjet Printed Graphene for Microsupercapacitors on Arbitrary Substrates
2019 (English)In: ACS Applied Energy Materials, ISSN 2574-0962, Vol. 2, no 1, p. 158-163Article in journal (Refereed) Published
Abstract [en]

Significant research interest is being devoted to exploiting the properties of graphene but the difficult integration on various substrates limits its use. In this regard, we developed a transfer technique that allows the direct deposition of inkjet printed graphene devices on arbitrary substrates, even 3D objects and living plants. With this technique, we fabricated micro-supercapacitors, which exhibited good adhesion on almost all substrates and no performance degradation induced by the process. Specifically, the microsupercapacitor on an orchid leaf showed an areal capacitance as high as 441 mu F cm(-2) and a volumetric capacitance of 1.16 F cm(-3). This technique can boost the use of graphene in key technological applications, such as self powered epidermal electronics and environmental monitoring systems.

Place, publisher, year, edition, pages
American Chemical Society (ACS), 2019
Keywords
graphene, wet transfer, inkjet printing, microsupercapacitors, arbitrary substrates
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-245956 (URN)10.1021/acsaem.8b01225 (DOI)000458706900019 ()
Note

QC 20190313

Available from: 2019-03-13 Created: 2019-03-13 Last updated: 2019-08-16Bibliographically approved
Kajihara, J., Kuroki, S.-I. -., Ishikawa, S., Maeda, T., Sezaki, H., Makino, T., . . . Zetterling, C.-M. (2018). 4H-SiC pMOSFETs with al-doped S/D and NbNi silicide ohmic contacts. In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017: . Paper presented at 17 September 2017 through 22 September 2017 (pp. 423-427). Trans Tech Publications
Open this publication in new window or tab >>4H-SiC pMOSFETs with al-doped S/D and NbNi silicide ohmic contacts
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2018 (English)In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, p. 423-427Conference paper, Published paper (Refereed)
Abstract [en]

4H-SiC pMOSFETs with Al-doped S/D and NbNi silicide ohmic contacts were demonstrated and were characterized at up to a temperature of 200°C. For the pMOSFETs, silicides on p-type 4H-SiC with Nb/Ni stack, Nb-Ni Alloy, Ni and Nb/Ti were investigated, and the Nb/Ni stack silicide with the contact resistance of 5.04×10-3 Ωcm2 were applied for the pMOSFETs.

Place, publisher, year, edition, pages
Trans Tech Publications, 2018
Keywords
4H-SiC, Harsh environment electronics, Nickel, Niobium, Ohmic contact, pMOSFET, Binary alloys, Electric contactors, MOSFET devices, Nickel alloys, Niobium alloys, Ohmic contacts, Silicides, Titanium alloys, Al doped, Harsh environment, Ni alloys, p-MOSFETs, P-type 4H-SiC, Silicon carbide
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-236375 (URN)10.4028/www.scientific.net/MSF.924.423 (DOI)2-s2.0-85049023373 (Scopus ID)9783035711455 (ISBN)
Conference
17 September 2017 through 22 September 2017
Note

QC 20181105

Available from: 2018-11-05 Created: 2018-11-05 Last updated: 2018-11-05Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-5845-3032

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