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Östling, M. (2024). The Status of WBG Devices Towards Net-Zero Solutions. In: 2024 IEEE 17th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024: . Paper presented at 17th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024, Zhuhai, China, October 22-25, 2024. Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>The Status of WBG Devices Towards Net-Zero Solutions
2024 (English)In: 2024 IEEE 17th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024, Institute of Electrical and Electronics Engineers (IEEE) , 2024Conference paper, Published paper (Refereed)
Abstract [en]

The world is facing a dramatic increase in the need for electricity and needs to battle the ever-increasing carbon dioxide emissions. New, more efficient, wide bandgap power electronics devices are developed to enable the urgent plans towards net-zero loss in electricity production, distribution and consumption. These devices will be very important pieces in the worldwide puzzle to enable fossil free electricity production, distribution and consumption. This paper discusses the status of wide bandgap device technology in the perspective of maturity of the devices for roll-out and implementation for industrial commercial use.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2024
Keywords
Device applications, Device performance, Efficiency, Wide bandgap devices
National Category
Energy Systems
Identifiers
urn:nbn:se:kth:diva-360557 (URN)10.1109/ICSICT62049.2024.10831121 (DOI)2-s2.0-85218142636 (Scopus ID)
Conference
17th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024, Zhuhai, China, October 22-25, 2024
Note

Part of ISBN 9798350361834

QC 20250227

Available from: 2025-02-26 Created: 2025-02-26 Last updated: 2025-02-27Bibliographically approved
Li, J. & Östling, M. (2023). Photodetectors Based on Emerging Materials. In: Massimo Rudan, Rossella Brunetti, Susanna Reggiani (Ed.), Springer Handbook of Semiconductor Devices: (pp. 777-805). Springer Nature
Open this publication in new window or tab >>Photodetectors Based on Emerging Materials
2023 (English)In: Springer Handbook of Semiconductor Devices / [ed] Massimo Rudan, Rossella Brunetti, Susanna Reggiani, Springer Nature , 2023, p. 777-805Chapter in book (Refereed)
Abstract [en]

Photodetectors that convert light into electrical signals have become an indispensable element for a large number of technologies to enable extensive applications, ranging from optical communications to advanced imaging and motion detection, to automotive industry particularly including self-driving cars, and to astronomy and space exploration under harsh environment. The present photodetector market is predominated by silicon (CMOS-based) photodetectors. With the continuous growth of application areas, highly desired are photodetectors of higher performance in terms of speed, efficiency, detectable wavelength range, and integrability with semiconductor technology. These necessitate the development of new photodetectors based on special materials, rather than the conventional silicon single crystals, as building blocks for various advanced photodetection platforms. To this end, we summarize in this chapter the recent status of advanced photodetectors based on the emerging material, graphene. Our discussion includes the performance metrics, working mechanisms, practical implementation, as well as opportunities and challenges, for graphene-based photodetectors. 

Place, publisher, year, edition, pages
Springer Nature, 2023
Series
Springer Handbooks, ISSN 2522-8692, E-ISSN 2522-8706
Keywords
3D substrates, Charge neutrality point, Graphene, Heterostructure, Optical cavity, Photodetection mechanism, Photodetectors, Waveguide
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-329008 (URN)10.1007/978-3-030-79827-7_21 (DOI)2-s2.0-85142031315 (Scopus ID)
Note

QC 20230614

Available from: 2023-06-14 Created: 2023-06-14 Last updated: 2023-06-14Bibliographically approved
Zurauskaite, L., Östling, M. & Hellström, P.-E. (2021). Improvement on Ge/GeOx/Tm2O3/HfO2 Gate Performance by Forming Gas Anneal. In: : . Paper presented at IEEE 51st European Solid-State Device Research Conference ESSDERC 2021, Grenoble, France [virtual] 13-17 September 2021. Institute of Electrical and Electronics Engineers IEEE
Open this publication in new window or tab >>Improvement on Ge/GeOx/Tm2O3/HfO2 Gate Performance by Forming Gas Anneal
2021 (English)Conference paper, Published paper (Refereed)
Abstract [en]

The improvement of forming gas anneal (10 % H2 in N2) at 400 °C on electrical properties of Ge/GeOx/Tm2O3/HfO2 gate stacks is investigated. It is found that forming gas anneal effectively suppresses fixed charge density, oxide trap density and interface state density. Hydrogen is demonstrated to efficiently passivate the negative fixed charge density and reduce the global variability of the flatband voltage down to 90 mV over a wafer. A forming gas anneal is also found to reduce equivalent oxide thickness in scaled gate stacks.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers IEEE, 2021
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-302647 (URN)
Conference
IEEE 51st European Solid-State Device Research Conference ESSDERC 2021, Grenoble, France [virtual] 13-17 September 2021
Note

QC 20210930

Available from: 2021-09-28 Created: 2021-09-28 Last updated: 2022-06-25Bibliographically approved
Zurauskaite, L., Östling, M. & Hellström, P.-E. (2021). Improvement on Ge/GeOx/Tm2O3/HfO2 Gate Performance by Forming Gas Anneal. In: IEEE 51ST EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2021): . Paper presented at IEEE 51st European Solid-State Device Research Conference (ESSDERC), SEP 06-09, 2021, ELECTR NETWORK (pp. 227-230). IEEE
Open this publication in new window or tab >>Improvement on Ge/GeOx/Tm2O3/HfO2 Gate Performance by Forming Gas Anneal
2021 (English)In: IEEE 51ST EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2021), IEEE , 2021, p. 227-230Conference paper, Published paper (Refereed)
Abstract [en]

The improvement of forming gas anneal (10 % H-2 in N-2) at 400 degrees C on electrical properties of Ge/GeOx/Tm2O3/HfO2 gate stacks is investigated. It is found that forming gas anneal effectively suppresses fixed charge density, oxide trap density and interface state density. Hydrogen is demonstrated to efficiently passivate the negative fixed charge density and reduce the global variability of the Hatband voltage down to 90 mV over a safer. A forming gas anneal is also found to reduce equivalent oxide thickness in scaled gate stacks.

Place, publisher, year, edition, pages
IEEE, 2021
Series
Proceedings of the European Solid-State Device Research Conference, ISSN 1930-8876
Keywords
germanium, Tm2O3, MOS, high-k, interface state density, fired charge density, forming gas anneal
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering Atom and Molecular Physics and Optics Other Engineering and Technologies
Identifiers
urn:nbn:se:kth:diva-312766 (URN)10.1109/ESSDERC53440.2021.9631773 (DOI)000790809500053 ()2-s2.0-85123430222 (Scopus ID)
Conference
IEEE 51st European Solid-State Device Research Conference (ESSDERC), SEP 06-09, 2021, ELECTR NETWORK
Note

Part of proceedings: ISBN 978-1-6654-3748-6

Not duplicate with DiVA 1598155

QC 20220523

Available from: 2022-05-23 Created: 2022-05-23 Last updated: 2025-02-10Bibliographically approved
Hou, S., Shakir, M., Hellström, P.-E., Malm, B. G., Zetterling, C.-M. & Östling, M. (2020). A Silicon Carbide 256 Pixel UV Image Sensor Array Operating at 400 degrees C. IEEE Journal of the Electron Devices Society, 8(1), 116-121
Open this publication in new window or tab >>A Silicon Carbide 256 Pixel UV Image Sensor Array Operating at 400 degrees C
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2020 (English)In: IEEE Journal of the Electron Devices Society, E-ISSN 2168-6734, Vol. 8, no 1, p. 116-121Article in journal (Refereed) Published
Abstract [en]

An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part has 256 ( $16\times 16$ ) pixels. The digital circuit part for row and column selection contains two 4-to-16 decoders and one 8-bit counter. The digital circuits are designed in transistor-transistor logic (TTL). The entire circuit has 1959 transistors. It is the first demonstration of SiC opto-electronic on-chip integration. The function of the image sensor up to 400 degrees C has been verified by taking photos of the spatial patterns masked from UV light. The image sensor would play a significant role in UV photography, which has important applications in astronomy, clinics, combustion detection and art.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2020
Keywords
Silicon carbide (SiC), image sensor, ultraviolet (UV), photodiode, high temperature, bipolar junction transistor (BJT), transistor-transistor logic (TTL)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-270881 (URN)10.1109/JEDS.2020.2966680 (DOI)000515658000001 ()2-s2.0-85079349461 (Scopus ID)
Note

QC 20200325

Available from: 2020-03-25 Created: 2020-03-25 Last updated: 2023-02-06Bibliographically approved
Fan, X., Smith, A. D., Forsberg, F., Wagner, S., Schröder, S., Akbari, S. S., . . . Niklaus, F. (2020). Manufacture and characterization of graphene membranes with suspended silicon proof masses for MEMS and NEMS applications. MICROSYSTEMS & NANOENGINEERING, 6(1), Article ID 17.
Open this publication in new window or tab >>Manufacture and characterization of graphene membranes with suspended silicon proof masses for MEMS and NEMS applications
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2020 (English)In: MICROSYSTEMS & NANOENGINEERING, ISSN 2055-7434, Vol. 6, no 1, article id 17Article in journal (Refereed) Published
Abstract [en]

Graphene's unparalleled strength, chemical stability, ultimate surface-to-volume ratio and excellent electronic properties make it an ideal candidate as a material for membranes in micro- and nanoelectromechanical systems (MEMS and NEMS). However, the integration of graphene into MEMS or NEMS devices and suspended structures such as proof masses on graphene membranes raises several technological challenges, including collapse and rupture of the graphene. We have developed a robust route for realizing membranes made of double-layer CVD graphene and suspending large silicon proof masses on membranes with high yields. We have demonstrated the manufacture of square graphene membranes with side lengths from 7 mu m to 110 mu m, and suspended proof masses consisting of solid silicon cubes that are from 5 mu mx5 mu mx16.4 mu m to 100 mu mx100 mu mx16.4 mu m in size. Our approach is compatible with wafer-scale MEMS and semiconductor manufacturing technologies, and the manufacturing yields of the graphene membranes with suspended proof masses were >90%, with >70% of the graphene membranes having >90% graphene area without visible defects. The measured resonance frequencies of the realized structures ranged from tens to hundreds of kHz, with quality factors ranging from 63 to 148. The graphene membranes with suspended proof masses were extremely robust, and were able to withstand indentation forces from an atomic force microscope (AFM) tip of up to 7000nN. The proposed approach for the reliable and large-scale manufacture of graphene membranes with suspended proof masses will enable the development and study of innovative NEMS devices with new functionalities and improved performances.

Place, publisher, year, edition, pages
NATURE PUBLISHING GROUP, 2020
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-273501 (URN)10.1038/s41378-019-0128-4 (DOI)000528968400001 ()34567632 (PubMedID)2-s2.0-85083758503 (Scopus ID)
Note

QC 20200520

Available from: 2020-05-20 Created: 2020-05-20 Last updated: 2022-06-26Bibliographically approved
Zurauskaite, L., Hellström, P.-E. & Östling, M. (2020). Process Conditions for Low Interface State Density in Si-passivated Ge Devices with TmSiO Interfacial Layer. ECS Journal of Solid State Science and Technology, 9(12), Article ID 125009.
Open this publication in new window or tab >>Process Conditions for Low Interface State Density in Si-passivated Ge Devices with TmSiO Interfacial Layer
2020 (English)In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 9, no 12, article id 125009Article in journal (Refereed) Published
Abstract [en]

In this work we study the epitaxial Si growth with Si2H6 for Ge surface passivation in CMOS devices. The Si-caps are grown on Ge in the hydrogen desorption limited regime at a nominal temperature of 400 degrees C. We evaluate the process window for the interface state density and show that there is an optimal Si-cap thickness between 8 and 9 monolayers for D-it < 510(11) cm(-2) eV(-1). Moreover, we discuss the strong impact of the Si-cap growth time and temperature on the interface state density, which arises from the Si thickness dependence on these growth parameters. Furthermore, we successfully transfer a TmSiO/Tm2O3/HfO2 gate stack process from Si to Ge devices with optimized Si-cap, yielding interface state density of 310(11) eV(-1) cm(-2) and a significant improvement in oxide trap density compared to GeOx passivation.

Place, publisher, year, edition, pages
The Electrochemical Society, 2020
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-289536 (URN)10.1149/2162-8777/abd48c (DOI)000605364100001 ()2-s2.0-85100150407 (Scopus ID)
Note

QC 20210203

Available from: 2021-02-03 Created: 2021-02-03 Last updated: 2024-03-18Bibliographically approved
Garidis, K., Abedin, A., Asadollahi, A., Hellström, P.-E. & Östling, M. (2020). Selective epitaxial growth of in situ doped SiGe on bulk Ge for p+/n junction formation. Electronics, 9(4), Article ID 578.
Open this publication in new window or tab >>Selective epitaxial growth of in situ doped SiGe on bulk Ge for p+/n junction formation
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2020 (English)In: Electronics, E-ISSN 2079-9292, Vol. 9, no 4, article id 578Article in journal (Refereed) Published
Abstract [en]

Epitaxial in situ doped Si0.73Ge0.27 alloys were grown selectively on patterned bulk Ge and bulk Si wafers. Si0.73Ge0.27 layers with a surface roughness of less than 3 nm were demonstrated. Selectively grown p+Si0.73Ge0.27 layers exhibited a resistivity of 3.5 mΩcm at a dopant concentration of 2.5 × 1019 boron atoms/cm3. P+/n diodes were fabricated by selectively growing p+-Si0.73Ge0.27 on n-doped bulk Ge and n-doped Si wafers, respectively. The geometrical leakage current contribution shifts from the perimeter to the bulk as the diode sizes increase. Extracted near midgap activation energies are similar to p+/n Ge junctions formed by ion implantation. This indicates that the reverse leakage current in p+/n Ge diodes fabricated with various doping methods, could originate from the same trap-assisted mechanism. Working p+/n diodes on Ge bulk substrates displayed a reverse current density as low as 2.2·10−2 A/cm2 which was found to be comparable to other literature data. The layers developed in this work can be used as an alternative method to form p+/n junctions on Ge substrates, showing comparable junction leakage results to ion implantation approaches.

Place, publisher, year, edition, pages
MDPI AG, 2020
Keywords
Diode, Epitaxy, Germanium, Junction, Selective, SiGe
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-277241 (URN)10.3390/electronics9040578 (DOI)000539533200037 ()2-s2.0-85083102766 (Scopus ID)
Note

QC 20200702

Available from: 2020-07-02 Created: 2020-07-02 Last updated: 2022-06-26Bibliographically approved
Zurauskaite, L., Abedin, A., Hellström, P.-E. & Östling, M. (2020). Si-passivated Ge Gate stacks with low interface state and oxide trap densities using thulium silicate. In: ECS Transactions: . Paper presented at Pacific Rim Meeting on Electrochemical and Solid State Science 2020, PRiME 200, 4 October 2020 through 9 October 2020 (pp. 387-393). IOP Publishing Ltd, 98(5)(5)
Open this publication in new window or tab >>Si-passivated Ge Gate stacks with low interface state and oxide trap densities using thulium silicate
2020 (English)In: ECS Transactions, IOP Publishing Ltd , 2020, Vol. 98(5), no 5, p. 387-393Conference paper, Published paper (Refereed)
Abstract [en]

Ultra-thin epitaxially grown Si layers have been used for Ge surface passivation in CMOS devices utilizing standard silicon SiO2/HfO2 gate stack. In this work, we propose a high-k TmSiO interfacial layer, which has shown excellent performance on Si, instead of the chemical SiO2. We successfully transfer a TmSiO/Tm2O3/HfO2 gate stack from silicon to Si-passivated Ge devices, yielding interface state density of 3·1011 eV-1cm-2, which is comparable to GeOx passivation. Moreover, Si-capped Ge gates with TmSiO interfacial layer achieve significant improvement in oxide trap density compared to GeOx passivation, exhibiting a potential for superior reliability. We further investigate the robustness of Si layer growth process and show that small (±3 °C) variations of growth temperature can be detrimental to the interface state density of the gate stacks.

Place, publisher, year, edition, pages
IOP Publishing Ltd, 2020
Keywords
Germanium compounds, Interface states, Logic gates, Si-Ge alloys, Silica, Silicates, Silicon, Silicon oxides, Thulium compounds, CMOS devices, Epitaxially grown, Gate stacks, Ge surfaces, Interface state density, Interfacial layer, Oxide trap density, Ultra-thin, Passivation
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-285309 (URN)10.1149/09805.0387ecst (DOI)2-s2.0-85092606438 (Scopus ID)
Conference
Pacific Rim Meeting on Electrochemical and Solid State Science 2020, PRiME 200, 4 October 2020 through 9 October 2020
Note

QC 20201202

Available from: 2020-12-02 Created: 2020-12-02 Last updated: 2024-01-10Bibliographically approved
Inoue, J., Kuroki, S.-I. -., Ishikawa, S., Maeda, T., Sezaki, H., Makino, T., . . . Zetterling, C.-M. (2019). 4H-SIC trench pMOSFETs for high-frequency CMOS inverters. In: Silicon Carbide and Related Materials 2018: . Paper presented at 12th European Conference on Silicon Carbide and Related Materials, ECSCRM 2018, 2-6 September 2018, Birmingham, United Kingdom (pp. 837-840). Trans Tech Publications Ltd
Open this publication in new window or tab >>4H-SIC trench pMOSFETs for high-frequency CMOS inverters
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2019 (English)In: Silicon Carbide and Related Materials 2018, Trans Tech Publications Ltd , 2019, p. 837-840Conference paper, Published paper (Refereed)
Abstract [en]

Low-parasitic-capacitance 4H-SiC pMOSFETs were demonstrated for high-frequency CMOS inverters. In these pMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain capacitance) were investigated and low parasitic capacitance was achieved by the trench gate structure.

Place, publisher, year, edition, pages
Trans Tech Publications Ltd, 2019
Series
Materials Science Forum, ISSN 1662-9752 ; 963
Keywords
4H-SiC, Harsh environment electronics, Overlapping capacitance, PMOSFET, Capacitance, CMOS integrated circuits, MOSFET devices, Device characteristics, Gate-drain capacitance, Harsh environment, High frequency HF, Parasitic capacitance, Trench gate structures, Silicon carbide
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-262430 (URN)10.4028/www.scientific.net/MSF.963.837 (DOI)2-s2.0-85071890235 (Scopus ID)
Conference
12th European Conference on Silicon Carbide and Related Materials, ECSCRM 2018, 2-6 September 2018, Birmingham, United Kingdom
Note

QC 20191104

Part of ISBN 9783035713329

Available from: 2019-11-04 Created: 2019-11-04 Last updated: 2024-10-28Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-5845-3032

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