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Ebrahimi, Masoumeh
Publications (10 of 25) Show all publications
Ebrahimi, M., Kelati, A., Nkonoki, E., Kondoro, A., Rwegasira, D., Ben Dhaou, I., . . . Tenhunen, H. (2019). Creation of CERID: Challenge, Education, Research, Innovation, and Deployment: in the context of smart MicroGrid. In: : . Paper presented at IST-Africa Week Conference (IST-Africa).
Open this publication in new window or tab >>Creation of CERID: Challenge, Education, Research, Innovation, and Deployment: in the context of smart MicroGrid
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2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

The iGrid project deals with the design and implementation of a solar-powered smart microgrid to supply electric power to small rural communities. In this paper, we discuss the roadmap of the iGrid project, which forms by merging the roadmaps of KIC (knowledge and Innovation Community) and CDE (Challenge-Driven Education). We introduce and explain a five-gear chain as Challenge, Education, Research, Innovation, and Deployment, called CERID, to reach the main goals of this project. We investigate the full chain in the iGrid project, which is established between KTH Royal Institute of Technology (Sweden) and University of Dar es Salam (Tanzania). We introduce the key stakeholders and explain how CERID goals can be accomplished in higher educations and through scientific research. Challenges are discussed, some innovative ideas are introduced and deployment solutions are recommended.

Keywords
knowledge and Innovation Community, challenge-driven educations, smart microgrid, innovation and business models.
National Category
Pedagogical Work Pedagogy Learning
Identifiers
urn:nbn:se:kth:diva-255686 (URN)10.23919/ISTAFRICA.2019.8764845 (DOI)978-1-905824-63-2 (ISBN)
Conference
IST-Africa Week Conference (IST-Africa)
Note

QC 20190819

Available from: 2019-08-08 Created: 2019-08-08 Last updated: 2019-08-19Bibliographically approved
Wang, J., Ebrahimi, M., Huang, L., Xie, X., Li, Q., Li, G. & Jantsch, A. (2019). Efficient Design-for-Test Approach for Networks-on-Chip. I.E.E.E. transactions on computers (Print), 68(2), 198-213
Open this publication in new window or tab >>Efficient Design-for-Test Approach for Networks-on-Chip
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2019 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 68, no 2, p. 198-213Article in journal (Refereed) Published
Abstract [en]

To achieve high reliability in on-chip networks, it is necessary to test the network continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the number of affected packets can be minimized. However, BISTcauses significant performance loss due to data dependencies. We propose EsyTest, a comprehensive test strategy with minimized influence on system performance. EsyTest tests the data path and the control path separately. The data path test starts periodically, but the actual test performs in the free time slots to avoid deactivating the router for testing. A reconfigurable router architecture and an adaptive fault-tolerant routing algorithm are proposed to guarantee the access to the processing core when the associated router is under test. During the whole test procedure of the network, all processing cores are accessible, and thus the system performance is maintained during the test. At the same time, EsyTest provides a full test coverage for the NoC and a better hardware compatibility comparing with the existing test strategies. Under the PARSEC benchmark and different test frequencies, the execution time increases less than 5 percent at the cost of 9.9 percent more area and 4.6 percent more power in comparison with the execution where no test procedure is applied.

Place, publisher, year, edition, pages
IEEE Computer Society Digital Library, 2019
Keywords
Network-on-chip, non-blocking testing, reliability monitoring, reconfigurable router architecture, adaptive routing algorithm, built-in self-test
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-243937 (URN)10.1109/TC.2018.2865948 (DOI)000456176200004 ()2-s2.0-85051797924 (Scopus ID)
Note

QC 20190306

Available from: 2019-03-06 Created: 2019-03-06 Last updated: 2019-08-15Bibliographically approved
Chen, K.-C. (., Ebrahimi, M., Wang, T.-Y. & Yang, Y.-C. (2019). NoC-based DNN Accelerator: A Future Design Paradigm. In: : . Paper presented at International Symposium on Networks-on-Chip (NOCS'19).
Open this publication in new window or tab >>NoC-based DNN Accelerator: A Future Design Paradigm
2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Deep Neural Networks (DNN) have shown significant advantagesin many domains such as pattern recognition, prediction, and controloptimization. The edge computing demand in the Internet-of-Things era has motivated many kinds of computing platforms toaccelerate the DNN operations. The most common platforms areCPU, GPU, ASIC, and FPGA. However, these platforms suffer fromlow performance (i.e., CPU and GPU), large power consumption(i.e., CPU, GPU, ASIC, and FPGA), or low computational flexibilityat runtime (i.e., FPGA and ASIC). In this paper, we suggest theNoC-based DNN platform as a new accelerator design paradigm.The NoC-based designs can reduce the off-chip memory accessesthrough a flexible interconnect that facilitates data exchange betweenprocessing elements on the chip. We first comprehensivelyinvestigate conventional platforms and methodologies used in DNNcomputing. Then we study and analyze different design parametersto implement the NoC-based DNN accelerator. The presentedaccelerator is based on mesh topology, neuron clustering, randommapping, and XY-routing. The experimental results on LeNet, MobileNet,and VGG-16 models show the benefits of the NoC-basedDNN accelerator in reducing off-chip memory accesses and improvingruntime computational flexibility.

Keywords
Network-on-Chip (NoC), Deep Neural Network (DNN), CNN, RNN, Accelerators, Routing Algorithms, Mapping Algorithms, Neural Network Simulator
National Category
Embedded Systems Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-255684 (URN)10.1145/3313231.3352376 (DOI)978-1-4503-6700-4 (ISBN)
Conference
International Symposium on Networks-on-Chip (NOCS'19)
Note

QC 20190819

Available from: 2019-08-08 Created: 2019-08-08 Last updated: 2019-08-19Bibliographically approved
Zhan, J., Huang, L., Wang, J., Ebrahimi, M. & Li, Q. (2019). Online Path-based Test Method for Network-on-Chip. In: 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS): . Paper presented at IEEE International Symposium on Circuits and Systems (IEEE ISCAS), MAY 26-29, 2019, Sapporo, JAPAN. IEEE
Open this publication in new window or tab >>Online Path-based Test Method for Network-on-Chip
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2019 (English)In: 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2019Conference paper, Published paper (Refereed)
Abstract [en]

A considerable amount of routers and links remains idle after each mapping application onto the Network-on-Chip based many-core systems. Online path-based test method is a kind of self-test for these idle components. In this paper, a path-based fabric for NoC is firstly proposed. A path serves as the basic component, covering one link and its associated control logic in the routers. One possibility is to apply fault detection on the idle paths, while the other paths continue to operate normally. Moreover, this paper details the hardware implementation, targeting the stuck-at and bridging faults. It suggests a good trade-off between fault coverage, hardware overhead and test time. Experimental results show that the approach achieves 93% of the stuck-at faults in control unit and cover 100% of the stuck-at and bridging faults on the global link within 256 clock cycles.

Place, publisher, year, edition, pages
IEEE, 2019
Series
IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-260223 (URN)10.1109/ISCAS.2019.8702409 (DOI)000483076401087 ()2-s2.0-85066783884 (Scopus ID)978-1-7281-0397-6 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (IEEE ISCAS), MAY 26-29, 2019, Sapporo, JAPAN
Note

QC 20190927

Available from: 2019-09-27 Created: 2019-09-27 Last updated: 2019-09-27Bibliographically approved
Jiang, S., Wu, Q., Chen, S., Zhan, J., Wang, J., Ebrahimi, M. & Huang, L. (2019). Testing aware dynamic mapping for path-centric network-on-chip test. Integration, 67, 134-143
Open this publication in new window or tab >>Testing aware dynamic mapping for path-centric network-on-chip test
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2019 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 67, p. 134-143Article in journal (Refereed) Published
Abstract [en]

With the aggressive scaling of submicron technology, intermittent faults are becoming one of the limiting factors in achieving high reliability in Network-on-Chip (NoC). Increasing test frequency is necessary to detect intermittent faults, which in turn interrupts the execution of applications. On the other hand, the primary goal of traditional mapping algorithms is to allocate applications to the NoC platform, ignoring the test requirement. In this paper, we propose a novel testing-aware mapping algorithm (TAMA) for NoC, targeting intermittent faults on the paths between crossbars. In this approach, the idle paths are identified, and the components between two crossbars are tested when the application is mapped to the platform. The components can be tested if there is enough time from the time when the application leaves the platform to the time when a new application enters it. The mapping algorithm is tuned to give a higher priority to the tested paths in the next application mapping, which leaves enough time to test the links and the belonging components that have not been tested in the expected time. Experiment results show that the proposed testing-aware mapping algorithm leads to a significant improvement over FF(Fiexitrst Free), NN(Nearest Neighbor), CoNA(Contiguous Neighborhood Allocation), and WeNA(Weighted-based Neighborhood Allocation).

Place, publisher, year, edition, pages
Elsevier, 2019
Keywords
Network-on-Chip, Mapping algorithm, Intermittent fault, On-line testing
National Category
Embedded Systems Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-254859 (URN)10.1016/j.vlsi.2018.11.009 (DOI)000473839600013 ()2-s2.0-85058048689 (Scopus ID)
Note

QC 20190710

Available from: 2019-07-05 Created: 2019-07-05 Last updated: 2019-07-29Bibliographically approved
Ebrahimi, M. & Daneshtalab, M. (2018). A General Methodology on Designing Acyclic Channel Dependency Graphs in Interconnection Networks. IEEE Micro, 38(3), 79-85
Open this publication in new window or tab >>A General Methodology on Designing Acyclic Channel Dependency Graphs in Interconnection Networks
2018 (English)In: IEEE Micro, ISSN 0272-1732, E-ISSN 1937-4143, Vol. 38, no 3, p. 79-85Article in journal (Refereed) Published
Abstract [en]

For the past three decades, the interconnection network has been developed based on two major theories, one by Dally and the other by Duato. In this article, we introduce EbDa with a simplified theoretical basis, which directly allows for designing an acyclic channel dependency graph and verifying algorithms on their freedom from deadlock. EbDa is composed of three theorems that enable extracting all allowable turns without dealing with turn models.

Place, publisher, year, edition, pages
IEEE Computer Society, 2018
National Category
Computer Sciences
Identifiers
urn:nbn:se:kth:diva-229028 (URN)10.1109/MM.2018.032271064 (DOI)000432316500010 ()2-s2.0-85046996689 (Scopus ID)
Funder
VinnovaSwedish Research Council
Note

QC 20180531

Available from: 2018-05-31 Created: 2018-05-31 Last updated: 2019-08-19Bibliographically approved
Huang, L., Chen, S., Wu, Q., Ebrahimi, M., Wang, J., Jiang, S. & Li, Q. (2018). A Lifetime-aware Mapping Algorithm to Extend MTTF of Networks-on-Chip. In: 2018 23rd Asia and South Pacific Design Automation Conference Proceedings (ASP-DAC): . Paper presented at 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), JAN 22-25, 2018, Jeju, South Korea (pp. 147-152). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>A Lifetime-aware Mapping Algorithm to Extend MTTF of Networks-on-Chip
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2018 (English)In: 2018 23rd Asia and South Pacific Design Automation Conference Proceedings (ASP-DAC), Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 147-152Conference paper, Published paper (Refereed)
Abstract [en]

Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology. This problem accelerates when combined with improper working conditions such as unbalanced components' utilization. Considering the mapping algorithms in the Networks-on-Chip domain, some routers/links might be frequently selected for mapping while others are underutilized. Consequently, the highly utilized components may age faster than others which results in disconnecting the related cores from the network. To address this issue, we propose a mapping algorithm, called lifetime-aware neighborhood allocation (LaNA), that takes the aging of components into account when mapping applications. The proposed method is able to balance the wear-out of NoC components, and thus extending the service time of NoC. We model the lifetime as a resource consumed over time and accordingly define the lifetime budget metric. LaNA selects a suitable node for mapping which has the maximum lifetime budget. Experimental results show that the lifetime-aware mapping algorithm could improve the minimal MTTF of NoC around 72.2%, 58.3%, 46.6% and 48.2% as compared to NN, CoNA, WeNA and CASqA, respectively.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Series
Asia and South Pacific Design Automation Conference Proceedings, ISSN 2153-6961
Keywords
many-core system, Network-on-Chip, mapping algorithm, lifetime reliability
National Category
Other Engineering and Technologies
Identifiers
urn:nbn:se:kth:diva-225090 (URN)000426987100024 ()2-s2.0-85045333574 (Scopus ID)978-1-5090-0602-1 (ISBN)
Conference
23rd Asia and South Pacific Design Automation Conference (ASP-DAC), JAN 22-25, 2018, Jeju, South Korea
Funder
VINNOVA
Note

QC 20180328

Available from: 2018-03-28 Created: 2018-03-28 Last updated: 2018-03-28Bibliographically approved
Charif, A., Coelho, A., Ebrahimi, M., Bagherzadeh, N. & Zergainoh, N.-E. (2018). First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip. IEEE transactions on computer, 67(10), 1430-1444
Open this publication in new window or tab >>First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip
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2018 (English)In: IEEE transactions on computer, ISSN 0018-9340, Vol. 67, no 10, p. 1430-1444Article in journal (Refereed) Published
Abstract [en]

3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3DNetwork-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connectedNoCs, in which only a few vertical TSV links are available, have been gaining relevance. To reliably route packets under suchconditions, we introduce a lightweight, efficient and highly resilient adaptive routing algorithm targeting partially vertically connected3D-NoCs named First-Last. It requires a very low number of virtual channels (VCs) to achieve deadlock-freedom (2 VCs in the Eastand North directions and 1 VC in all other directions), and guarantees packet delivery as long as one healthy TSV connecting all layersis available anywhere in the network. An improved version of our algorithm, named Enhanced-First-Last is also introduced and shownto dramatically improve performance under low TSV availability while still using less virtual channels than state-of-the-art algorithms. Acomprehensive evaluation of the cost and performance of our algorithms is performed to demonstrate their merits with respects toexisting solutions.

Keywords
network routing;network-on-chip;three-dimensional integrated circuits;virtual channels;healthy TSV;low TSV availability;packet delivery;3D Network-on-Chip;Enhanced-First-Last;TSV-based three-dimensional networks-on-chip;3D integration;through-silicon via;partially vertically connected 3D-NoCs;highly resilient adaptive routing algorithm;vertical TSV links;future multiprocessor chips;cost-effective adaptive routing solution;Routing;Through-silicon vias;Elevators;System recovery;Topology;Three-dimensional displays;Two dimensional displays;Network-on-Chip;3D NoC;3D integration;adaptive routing;TSV
National Category
Embedded Systems Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-254861 (URN)10.1109/TC.2018.2822269 (DOI)000444003700005 ()2-s2.0-85045190982 (Scopus ID)
Note

QC 20190813

Available from: 2019-07-05 Created: 2019-07-05 Last updated: 2019-08-13Bibliographically approved
Salamat, R., Khayambashi, M., Ebrahimi, M. & Bagherzadeh, N. (2018). LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification. I.E.E.E. transactions on computers (Print), 67(8), 1153-1166
Open this publication in new window or tab >>LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification
2018 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 67, no 8, p. 1153-1166Article in journal (Refereed) Published
Abstract [en]

2D-NoCs have been the mainstream approach used to interconnect multi-core systems. 3D-NoCs have emerged to compensate for deficiencies of 2D-NoCs such as long latency and power overhead. A low-latency routing algorithm for 3D-NoC is designed to accommodate high-speed communication between cores. Both simulation and analytical models are applied to estimate the communication latency of NoCs. Generally, simulations are time-consuming and slow down the design process. Analytical models provide, within a fraction of the time, nearly accurate results which can be used by simulation to fine-tune the design. In this paper, a high performance and adaptive routing algorithm has been proposed for partially connected 3D-NoCs. Latency of the routing algorithm under different traffic patterns, different number of elevators and different elevator assignment mechanisms are reported. An analytical model, tailored to the adaptivity of the algorithm and under low traffic scenarios, has been developed and the results have been verified by simulation. According to the results, simulation and analytical results are consistent within a 10 percent margin.

Place, publisher, year, edition, pages
IEEE Computer Society, 2018
Keywords
3D network-on-chip, routing algorithm, deadlock-free, queuing theory, analytical model, latency
National Category
Computer Engineering
Identifiers
urn:nbn:se:kth:diva-232751 (URN)10.1109/TC.2018.2801298 (DOI)000438724000007 ()2-s2.0-85041506447 (Scopus ID)
Note

QC 20180807

Available from: 2018-08-07 Created: 2018-08-07 Last updated: 2019-08-02Bibliographically approved
Ebrahimi, M., Chen, K.-C. -. & Reshadi, M. (2018). NoCArc 2018 Message from the Chairs. Paper presented at 20 October 2018. 11th International Workshop on Network on Chip Architectures, NoCArc 2018, Article ID 8541230.
Open this publication in new window or tab >>NoCArc 2018 Message from the Chairs
2018 (English)In: 11th International Workshop on Network on Chip Architectures, NoCArc 2018, article id 8541230Article in journal (Refereed) Published
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2018
National Category
Architecture
Identifiers
urn:nbn:se:kth:diva-247046 (URN)10.1109/NOCARC.2018.8541230 (DOI)2-s2.0-85059979020 (Scopus ID)
Conference
20 October 2018
Note

QC 20190625

Available from: 2019-06-25 Created: 2019-06-25 Last updated: 2019-06-25Bibliographically approved
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