Future meshed high-voltage direct current grids require modular multilevel converters with extended functionality. One of the most interesting new submodule topologies is the semi-full-bridge because it enables efficient handling of DC-side short circuits while having reduced power losses compared to an implementation with full-bridge submodules. However, the semi-full-bridge submodule requires the parallel connection of capacitors during normal operation which can cause a high redistribution current in case the voltages of the two submodule capacitors are not equal. The maximum voltage difference and resulting redistribution current have been studied analytically, by means of simulations and in a full-scale standalone submodule laboratory setup. The most critical parameter is the capacitance mismatch between the two capacitors. The experimental results from the full-scale prototype show that the redistribution current peaks at 500A if the voltage difference is 10V before paralleling and increases to 2500A if the difference is 40V. However, neglecting very unlikely cases, the maximum voltage difference predicted by simulations is not higher than 20-30V for the considered case. Among other measures, a balancing controller is proposed which reduces the voltage difference safely if a certain maximum value is surpassed. The operating principle of the controller is described in detail and verified experimentally on a down-scaled submodule within a modular multilevel converter prototype. It can be concluded that excessively high redistribution currents can be prevented. Consequently, they are no obstacle for using the semi-full-bridge submodule in future HVDC converters.

Implantation-free mesa-etched ultra-high-voltage (0.08 mm(2)) 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured, and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension is utilized to obtain a high and stable breakdown voltage without ion implantation. The open-base blocking voltage of 15.8 kV at a leakage current density of 0.1 mA/cm(2) is achieved. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared.

Converter cells for HVDC applications store large amounts of energy. This energy might be dissipated in a very short time in case of a shoot-through fault. Measures to avoid shoot-through or handle the extreme currents during a fault and prevent damage from neighboring components are essential to ensure a continued operation of the converter. With future high-voltage silicon carbide semiconductors, cell voltages can be increased leading to higher stored energy per cell. In cells with thyristor-based semiconductors, e.g. IGCTs, a di/dt reactor may have to be employed. This paper presents a method to handle the dissipated energy during shoot-through which makes use of the inherently needed di/dt reactor. The majority of the stored energy in the cell can be dissipated in a dedicated discharge loop formed by the reactor and an antiparallel bypass thyristor. After diverting the fault current into the dissipation loop, there is no current through any other component of the cell.

As regards modular multilevel converter submodules, a different number of switches may be involved in the transitions between voltage levels depending on the submodule type and choice of switching states. In this paper, an investigation of the average switching frequency associated with different choices of bypass states is performed for the semi-full-bridge submodule. Theoretical considerations and simulation results show that the average switching frequency per device can be halved by using the proposed alternative bypass state. Moreover, the switching losses can be reduced by up to 60%. Finally, a comparative study with the full-bridge submodule has been conducted.

This paper investigates the benefits of using high-voltage converter cells for transmission applications. These cells employ ultrahigh-voltage SiC bipolar power semiconductors, which are optimized for low conduction losses. The Modular Multilevel Converter with half-bridge cells is used as a test case. The results indicate a reduction of converter volume and complexity, while maintaining low losses and harmonic performance.

The surge current capability of the body-diode of SiC MOSFETs is experimentally analyzed in order to investigate the possibility of using SiC MOSFETs for HVDC applications. SiC MOSFET discrete devices and modules have been tested with surge currents up to 10 times the rated current and for durations up to 2 ms. Although the presence of stacking faults cannot be excluded, the experiments reveal that the failure may occur due to the latch-up of the parasitic n-p-n transistor located in the SiC MOSFET.

In this paper, the theoretical performance of ultra-high voltage Silicon Carbide (SiC) based devices are investigated. The SiC semiconductor device conduction power loss and switching power loss are predicted and compared with different modeling approaches, for SiC metal-oxide semiconductor field-effect transistors (MOSFETs) up to 20 kV and SiC gate turn-off (GTO) thyristors and SiC insulated-gate bipolar transistors (IGBTs) up to 50 kV. A parameter sensitivity analysis has been performed to observe the device power loss under various operating conditions, for instance current density, temperature and charge carrier lifetime. Also, the maximum allowed current density and maximum switching frequency for a maximum chip power dissipation limit of 300 W/cm(2) are investigated. The simulation results indicate that the SiC MOSFET has the highest current capability up to approximately 15 kV, while the SiC IGBT is suitable in the range of 15 kV to 35 kV, and thereafter the SiC GTO thyristor supersedes the loss performance from 35 kV to 50 kV.