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Ivanisevic, Nikola
Publications (6 of 6) Show all publications
Ivanisevic, N., Rodriguez, S. & Rusu, A. (2019). Impedance Spectroscopy Based on Linear System Identification. IEEE Transactions on Biomedical Circuits and Systems, 13(2), 396-402
Open this publication in new window or tab >>Impedance Spectroscopy Based on Linear System Identification
2019 (English)In: IEEE Transactions on Biomedical Circuits and Systems, ISSN 1932-4545, E-ISSN 1940-9990, Vol. 13, no 2, p. 396-402Article in journal (Refereed) Published
Abstract [en]

Impedance spectroscopy is a commonly used mea-surement technique for electrical characterization of a sample-under-test over a wide frequency range. Most measurementmethods employ a sine wave excitation generator, which implies apoint-by-point frequency sweep and a complex readout architec-ture. This paper presents a fast, wide-band, measurement methodfor impedance spectroscopy based on linear system identification.The main advantage of the proposed method is the low hardwarecomplexity, which consists of a 3-level pulse waveform, aninverting voltage amplifier and a general purpose ADC. A proof-of-concept prototype, which is implemented with off-the-shelfcomponents, achieves an estimation fit of approximately 96%.The prototype operation is validated electrically using knownRC component values and tested in real application conditions.

Place, publisher, year, edition, pages
IEEE, 2019
Keywords
Impedance spectroscopy, system identification, adaptive filtering, pseudo-random waveform, IIR filter, ARX.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-244757 (URN)10.1109/TBCAS.2019.2900584 (DOI)000462410800012 ()30794518 (PubMedID)2-s2.0-85061964097 (Scopus ID)
Funder
Swedish Research Council
Note

QC 20190301

Available from: 2019-02-25 Created: 2019-02-25 Last updated: 2019-04-23Bibliographically approved
Ivanisevic, N., Rodriguez, S. & Rusu, A. (2018). A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 05
Open this publication in new window or tab >>A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems
2018 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 05Article in journal (Refereed) Accepted
Abstract [en]

This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-229446 (URN)10.1109/TCSI.2018.2838135 (DOI)000448934700002 ()2-s2.0-85048023102 (Scopus ID)
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-06-04 Created: 2018-06-04 Last updated: 2019-04-12Bibliographically approved
Ivanisevic, N., Rodriguez, S. & Rusu, A. (2018). Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation. In: : . Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS) 2018. Florence, Italy: IEEE
Open this publication in new window or tab >>Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation
2018 (English)Conference paper, Published paper (Refereed)
Abstract [en]

A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is −133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

Place, publisher, year, edition, pages
Florence, Italy: IEEE, 2018
Series
IEEE International Symposium on Circuits and Systems (ISCAS), E-ISSN 2379-447X
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-229449 (URN)10.1109/ISCAS.2018.8351377 (DOI)000451218702062 ()2-s2.0-85057071679 (Scopus ID)978-1-5386-4881-0 (ISBN)978-1-5386-4882-7 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS) 2018
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-06-04 Created: 2018-06-04 Last updated: 2019-05-07Bibliographically approved
Chen, Y., Praamsma, L., Ivanisevic, N. & Leenaerts, D. M. (2017). A 40GHz PLL with -92.5dBc/Hz in-band phase noise and 104fs-RMS-jitter. In: Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium: . Paper presented at 2017 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2017, 4 June 2017 through 6 June 2017, Honolulu, HI (pp. 31-32). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>A 40GHz PLL with -92.5dBc/Hz in-band phase noise and 104fs-RMS-jitter
2017 (English)In: Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 31-32Conference paper, Published paper (Refereed)
Abstract [en]

This paper demonstrates a fully integrated low phase noise PLL at 40GHz, implemented in a 0.25-μm SiGe:C BiCMOS technology. An in-band phase noise improvement of 1.4dB to 3.2dB is measured across the locking range using the proposed double-gain PFD. The PLL achieves an in-band phase noise <-92.5dBc/Hz and an integrated RMS jitter of 104fs, a 25% improvement over conventional PFD. The reference spurs are <-73dBc across the whole locking range.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2017
Series
IEEE Radio Frequency Integrated Circuits Symposium, ISSN 1529-2517
Keywords
Ka-band, low phase noise, PFD, PLL, Jitter, Locks (fasteners), Phase locked loops, Radio waves, Semiconducting silicon, Fully integrated, In-band phase noise, Ka band, Locking range, Reference spur, RMS jitter, SiGe:C BiCMOS technology, Phase noise
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-216293 (URN)10.1109/RFIC.2017.7969009 (DOI)000426956400008 ()2-s2.0-85026850736 (Scopus ID)9781509046263 (ISBN)
Conference
2017 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2017, 4 June 2017 through 6 June 2017, Honolulu, HI
Note

QC 20171211

Available from: 2017-12-11 Created: 2017-12-11 Last updated: 2018-03-23Bibliographically approved
Ivanisevic, N., Rodriguez, S. & Rusu, A. (2017). Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach. In: 2017 IEEE Biomedical Circuits and Systems Conference, Turin, October 19-21, 2017: . Paper presented at 2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017, Politecnico di TorinoTorino, Italy, 19 October 2017 through 21 October 2017. Turin, Italy: Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach
2017 (English)In: 2017 IEEE Biomedical Circuits and Systems Conference, Turin, October 19-21, 2017, Turin, Italy: Institute of Electrical and Electronics Engineers (IEEE), 2017Conference paper, Published paper (Refereed)
Abstract [en]

Impedance spectroscopy is a low-cost sensing technique that is generating considerable interest in wearable and implantable biomedical applications since it can be efficiently integrated on a single microchip. In this paper, the fundamental characteristics of the most well-known system architectures are presented, and a more robust and hardware-efficient solution is proposed. An all-digital implementation based on adaptive filtering is used for identifying the impedance parameters of a sample-under-test. The coefficients of an infinite-impulse-response (IIR) filter are tuned by an adaptive algorithm based on pseudo-linear regression and output-error formulation. A three-level pseudorandom noise generator with a concave power spectral density is employed without deteriorating the nominal performance. Proof-of-concept has been verified with behavioral simulations.

Place, publisher, year, edition, pages
Turin, Italy: Institute of Electrical and Electronics Engineers (IEEE), 2017
Keywords
Adaptive algorithms, Clocks, Frequency measurement, Impedance, Impedance measurement, Spectroscopy, Systems architecture
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-225867 (URN)10.1109/BIOCAS.2017.8325148 (DOI)2-s2.0-85050013856 (Scopus ID)978-1-5090-5803-7 (ISBN)
Conference
2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017, Politecnico di TorinoTorino, Italy, 19 October 2017 through 21 October 2017
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-04-10 Created: 2018-04-10 Last updated: 2019-04-12Bibliographically approved
Ivanisevic, N., Rodriguez, S. & Rusu, A. (2016). A 96.4 dB High-Pass Delta-Sigma Modulator with Dynamic Biasing and Tree-Structured DEM. In: 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS): . Paper presented at 14th IEEE International New Circuits and Systems Conference (NEWCAS), JUN 26-29, 2016, Vancouver, CANADA. Vancouver, Canada: IEEE, Article ID 7604762.
Open this publication in new window or tab >>A 96.4 dB High-Pass Delta-Sigma Modulator with Dynamic Biasing and Tree-Structured DEM
2016 (English)In: 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), Vancouver, Canada: IEEE, 2016, article id 7604762Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a switched-capacitor high-pass delta-sigma modulator that can directly convert a chopper modulated signal to the digital domain. Low power consumption is achieved by employing inverter-based amplifiers and dynamic biasing in the first amplifier with relaxed slew-rate requirements as a result of the multi-bit quantization. The mismatch errors in the switched-capacitor DAC are first-order noise shaped by a tree-structured dynamic element matching encoder. Schematic level simulations show that the high-pass modulator achieves a peak SNDR of 96.4 dB and a SFDR of 101 dBc over a bandwidth of 300 Hz. The total estimated power consumption of the modulator is 19.56 mu W leading to a figure-of-merit of 0.6 pJ/conv.

Place, publisher, year, edition, pages
Vancouver, Canada: IEEE, 2016
Series
IEEE International New Circuits and Systems Conference
Keywords
delta-sigma, ADC, modulator, switched-capacitor, DEM, dynamic, element, matching
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-198993 (URN)10.1109/NEWCAS.2016.7604762 (DOI)000386900400028 ()2-s2.0-84999014708 (Scopus ID)978-1-4673-8900-6 (ISBN)
Conference
14th IEEE International New Circuits and Systems Conference (NEWCAS), JUN 26-29, 2016, Vancouver, CANADA
Funder
Swedish Research Council
Note

QC 20170116

Available from: 2017-01-16 Created: 2016-12-22 Last updated: 2019-04-12Bibliographically approved
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