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Publications (10 of 16) Show all publications
Hussain, M. W., Elahipanah, H., Zumbro, J. E., Rodriguez, S., Malm, B. G., Mantooth, H. A. & Rusu, A. (2019). A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications. IEEE Journal of the Electron Devices Society, 7(1), 191-195
Open this publication in new window or tab >>A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications
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2019 (English)In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 7, no 1, p. 191-195Article in journal (Refereed) Published
Abstract [en]

This brief presents a 59.5 MHz negative resistanceoscillator for high-temperature operation. The oscillator employs an in-house 4H-SiC BJT, integrated with the requiredcircuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room-temperature up to 400 C. The oscillator delivers an output◦power of 11.2 dBm into a 50 Ω load at 25 C, which decreases to 8.4 dBm at 400 C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased witha collector current of 35 mA from a 12 V supply and has amaximum DC power consumption of 431 mW.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2019
Keywords
4H-SiC BJT, high-temperature, LTCC, negative resistance, oscillator
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-245068 (URN)10.1109/JEDS.2018.2889638 (DOI)000460753000029 ()2-s2.0-85059455428 (Scopus ID)
Note

QC 20190311

Available from: 2019-03-05 Created: 2019-03-05 Last updated: 2019-10-17Bibliographically approved
Albertsson, D. I., Zahedinejad, M., Åkerman, J., Rodriguez, S. & Rusu, A. (2019). Compact Macrospin-Based Model of Three-Terminal Spin-Hall Nano Oscillators. IEEE transactions on magnetics, 55(10), Article ID 4003808.
Open this publication in new window or tab >>Compact Macrospin-Based Model of Three-Terminal Spin-Hall Nano Oscillators
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2019 (English)In: IEEE transactions on magnetics, ISSN 0018-9464, E-ISSN 1941-0069, Vol. 55, no 10, article id 4003808Article in journal (Refereed) Published
Abstract [en]

Emerging spin-torque nano oscillators (STNOs) and spin-Hall nano oscillators (SHNOs) are potential candidates for microwave applications. Recent advances in three-terminal magnetic tunnel junction (MTJ)-based SHNOs opened the possibility to develop more reliable and well-controlled oscillators, thanks to individual spin Hall-driven precession excitation and read-out paths. To develop hybrid systems by integrating three-terminal SHNOs and CMOS circuits, an electrical model able to capture the analog characteristics of three-terminal SHNOs is needed. This model needs to be compatible with current electric design automation (EDA) tools. This work presents a comprehensive macrospin-based model of three-terminal SHNOs able to describe the dc operating point, frequency modulation, phase noise, and output power. Moreover, the effect of voltage-controlled magnetic anisotropy (VCMA) is included. The model shows good agreement with experimental measurements and could be used in developing hybrid three-terminal SHNO/CMOS systems.

Place, publisher, year, edition, pages
IEEE Press, 2019
Keywords
Compact model, magnetic tunnel junction (MTJ), spin-Hall nano oscillator (SHNO)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-259715 (URN)10.1109/TMAG.2019.2925781 (DOI)000487191400001 ()
Funder
Swedish Research Council
Note

QC 20190930

Available from: 2019-09-20 Created: 2019-09-20 Last updated: 2019-10-11Bibliographically approved
Ivanisevic, N., Rodriguez, S. & Rusu, A. (2019). Impedance Spectroscopy Based on Linear System Identification. IEEE Transactions on Biomedical Circuits and Systems, 13(2), 396-402
Open this publication in new window or tab >>Impedance Spectroscopy Based on Linear System Identification
2019 (English)In: IEEE Transactions on Biomedical Circuits and Systems, ISSN 1932-4545, E-ISSN 1940-9990, Vol. 13, no 2, p. 396-402Article in journal (Refereed) Published
Abstract [en]

Impedance spectroscopy is a commonly used mea-surement technique for electrical characterization of a sample-under-test over a wide frequency range. Most measurementmethods employ a sine wave excitation generator, which implies apoint-by-point frequency sweep and a complex readout architec-ture. This paper presents a fast, wide-band, measurement methodfor impedance spectroscopy based on linear system identification.The main advantage of the proposed method is the low hardwarecomplexity, which consists of a 3-level pulse waveform, aninverting voltage amplifier and a general purpose ADC. A proof-of-concept prototype, which is implemented with off-the-shelfcomponents, achieves an estimation fit of approximately 96%.The prototype operation is validated electrically using knownRC component values and tested in real application conditions.

Place, publisher, year, edition, pages
IEEE, 2019
Keywords
Impedance spectroscopy, system identification, adaptive filtering, pseudo-random waveform, IIR filter, ARX.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-244757 (URN)10.1109/TBCAS.2019.2900584 (DOI)000462410800012 ()30794518 (PubMedID)2-s2.0-85061964097 (Scopus ID)
Funder
Swedish Research Council
Note

QC 20190301

Available from: 2019-02-25 Created: 2019-02-25 Last updated: 2019-04-23Bibliographically approved
Chaourani, P., Rodriguez, S., Hellström, P.-E. & Rusu, A. (2019). Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 27(2), 468-480
Open this publication in new window or tab >>Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines
2019 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, no 2, p. 468-480Article in journal (Refereed) Published
Abstract [en]

Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2019
Keywords
Area reduction, inductors, monolithic 3-D (M3D) radio-frequency/analog-mixed signal (RF/AMS) circuits, M3D integration, shielding
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-244530 (URN)10.1109/TVLSI.2018.2877132 (DOI)000458069300018 ()2-s2.0-85056564540 (Scopus ID)
Note

QC 20190403

Available from: 2019-04-03 Created: 2019-04-03 Last updated: 2019-05-22Bibliographically approved
Kargarrazi, S., Elahipanah, H., Rodriguez, S. & Zetterling, C.-M. (2018). 500 °c, High Current Linear Voltage Regulator in 4H-SiC BJT Technology. IEEE Electron Device Letters, 39(4), 548-551
Open this publication in new window or tab >>500 °c, High Current Linear Voltage Regulator in 4H-SiC BJT Technology
2018 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 4, p. 548-551Article in journal (Refereed) Published
Abstract [en]

This letter reports on a fully integrated 2-linear voltage regulator operational in a wide temperature range from 25 °C up to 500 °C fabricated in 4H-SiC technology. The circuit provides a stable output voltage with less than 1% variation in the entire temperature range. This letter demonstrates the first power supply solution providing both high-temperature (up to 500 °C) and high-load driving capabilities (up to 2).

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
Bipolar junction transistor (BJT), high-temperature IC, linear voltage regulator (LVR), silicon carbide (SiC)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-227638 (URN)10.1109/LED.2018.2805229 (DOI)000428689000022 ()2-s2.0-85041829681 (Scopus ID)
Funder
Swedish Foundation for Strategic Research Knut and Alice Wallenberg Foundation
Note

QC 20180514

Available from: 2018-05-14 Created: 2018-05-14 Last updated: 2018-05-14Bibliographically approved
Ivanisevic, N., Rodriguez, S. & Rusu, A. (2018). A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 05
Open this publication in new window or tab >>A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems
2018 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 05Article in journal (Refereed) Accepted
Abstract [en]

This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-229446 (URN)10.1109/TCSI.2018.2838135 (DOI)000448934700002 ()2-s2.0-85048023102 (Scopus ID)
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-06-04 Created: 2018-06-04 Last updated: 2019-04-12Bibliographically approved
Hussain, M. W., Elahipanah, H., Zumbro, J. E., Schröder, S., Rodriguez, S., Malm, B. G., . . . Rusu, A. (2018). A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology. IEEE Electron Device Letters, 39(6), 855-858
Open this publication in new window or tab >>A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology
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2018 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 6, p. 855-858Article in journal (Refereed) Accepted
Abstract [en]

This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.

Place, publisher, year, edition, pages
IEEE Press, 2018
Keywords
4H-SiC BJTs, high-temperature, RF, mixer
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-228486 (URN)10.1109/LED.2018.2829628 (DOI)000437086800018 ()2-s2.0-85045754083 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation
Note

QC 20180601

Available from: 2018-05-25 Created: 2018-05-25 Last updated: 2019-04-24Bibliographically approved
Chaourani, P., Stathis, D., Rodriguez, S., Hellström, P.-E. & Rusu, A. (2018). A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors. In: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S): . Paper presented at IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE conference proceedings
Open this publication in new window or tab >>A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors
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2018 (English)In: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE conference proceedings, 2018Conference paper, Published paper (Refereed)
Abstract [en]

The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2018
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-235831 (URN)000462960700020 ()2-s2.0-85063138253 (Scopus ID)
Conference
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
Note

QC 20181008

Available from: 2018-10-06 Created: 2018-10-06 Last updated: 2019-07-31Bibliographically approved
Hussain, M. W., Elahipanah, H., Schröder, S., Rodriguez, S., Malm, B. G., Östling, M. & Rusu, A. (2018). An Intermediate Frequency Amplifier for High-Temperature Applications. IEEE Transactions on Electron Devices, 65(4), 1411-1418
Open this publication in new window or tab >>An Intermediate Frequency Amplifier for High-Temperature Applications
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2018 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 65, no 4, p. 1411-1418Article in journal (Refereed) Accepted
Abstract [en]

This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than-7 and-11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base-collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
4H-silicon carbide (4H-SiC) bipolar junction transistors (BJTs), high temperature, intermediate frequency (IF) amplifiers, matching networks
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-227642 (URN)10.1109/TED.2018.2804392 (DOI)000427856300022 ()2-s2.0-85042860667 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation
Note

QC 20180509

Available from: 2018-05-09 Created: 2018-05-09 Last updated: 2019-04-24Bibliographically approved
Ivanisevic, N., Rodriguez, S. & Rusu, A. (2018). Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation. In: : . Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS) 2018. Florence, Italy: IEEE
Open this publication in new window or tab >>Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation
2018 (English)Conference paper, Published paper (Refereed)
Abstract [en]

A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is −133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

Place, publisher, year, edition, pages
Florence, Italy: IEEE, 2018
Series
IEEE International Symposium on Circuits and Systems (ISCAS), E-ISSN 2379-447X
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-229449 (URN)10.1109/ISCAS.2018.8351377 (DOI)000451218702062 ()2-s2.0-85057071679 (Scopus ID)978-1-5386-4881-0 (ISBN)978-1-5386-4882-7 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS) 2018
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-06-04 Created: 2018-06-04 Last updated: 2019-05-07Bibliographically approved
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Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0003-0565-9907

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