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Radamson, Henry H.
Publications (9 of 9) Show all publications
Wang, G., Luo, J., Qin, C., Liang, R., Xu, Y., Liu, J., . . . Ye, T. (2017). Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors. Nanoscale Research Letters, 12, Article ID 123.
Open this publication in new window or tab >>Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors
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2017 (English)In: Nanoscale Research Letters, ISSN 1931-7573, E-ISSN 1556-276X, Vol. 12, article id 123Article in journal (Refereed) Published
Abstract [en]

In this study, the integration of SiGe selective epitaxy on source/drain regions and high-k and metal gate for 22 nm node bulk pMOS transistors has been presented. Selective Si1-xGex growth (0.35 <= x <= 0.40) with boron concentration of 1-3 x 10(20) cm(-3) was used to elevate the source/drain. The main focus was optimization of the growth parameters to improve the epitaxial quality where the high-resolution x-ray diffraction (HRXRD) and energy dispersive spectrometer (EDS) measurement data provided the key information about Ge profile in the transistor structure. The induced strain by SiGe layers was directly measured by x-ray on the array of transistors. In these measurements, the boron concentration was determined from the strain compensation of intrinsic and boron-doped SiGe layers. Finally, the characteristic of transistors were measured and discussed showing good device performance.

Place, publisher, year, edition, pages
Springer, 2017
Keyword
22-nm PMOS, SiGe selective epitaxy, RPCVD, High-k and metal gate
National Category
Nano Technology
Identifiers
urn:nbn:se:kth:diva-204690 (URN)10.1186/s11671-017-1908-0 (DOI)000394542800004 ()28228008 (PubMedID)2-s2.0-85013155553 (Scopus ID)
Note

QC 20170602

Available from: 2017-06-02 Created: 2017-06-02 Last updated: 2017-06-02Bibliographically approved
Radamson, H. H., Luo, J., Qin, C., Yin, H., Zhu, H., Zhao, C. & Wang, G. (2017). Optimization of Selective Growth of SiGe for Source/Drain in 14nm and beyond Nodes FinFETs. International Journal of High Speed Electronics and Systems, 26(1-2), Article ID 1740003.
Open this publication in new window or tab >>Optimization of Selective Growth of SiGe for Source/Drain in 14nm and beyond Nodes FinFETs
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2017 (English)In: International Journal of High Speed Electronics and Systems, ISSN 0129-1564, Vol. 26, no 1-2, article id 1740003Article in journal (Refereed) Published
Abstract [en]

In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k &amp; metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 1020 cm-3. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.

Place, publisher, year, edition, pages
World Scientific Publishing Co. Pte Ltd, 2017
Keyword
FinFET, selective epitaxy growth, SiGe, Aspect ratio, Budget control, Epitaxial growth, Fins (heat exchange), Germanium, Hafnium oxides, High-k dielectric, Mapping, MOSFET devices, Silicon alloys, Synchrotron radiation, Tungsten, Boron concentrations, Electrical characteristic, High aspect ratio, Reciprocal space mapping, Strain distributions, Transistor structure, Atomic layer deposition
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-207307 (URN)10.1142/S0129156417400031 (DOI)2-s2.0-85013290773 (Scopus ID)
Note

QC 20170613

Available from: 2017-06-13 Created: 2017-06-13 Last updated: 2017-06-13Bibliographically approved
Wang, G., Luo, J., Liu, J., Yang, T., Xu, Y., Li, J., . . . Radamson, H. H. (2017). pMOSFETs Featuring ALD W Filling Metal Using SiH4 and B2H6 Precursors in 22 nm Node CMOS Technology. Nanoscale Research Letters, 12, Article ID 306.
Open this publication in new window or tab >>pMOSFETs Featuring ALD W Filling Metal Using SiH4 and B2H6 Precursors in 22 nm Node CMOS Technology
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2017 (English)In: Nanoscale Research Letters, ISSN 1931-7573, E-ISSN 1556-276X, Vol. 12, article id 306Article in journal (Refereed) Published
Abstract [en]

In this paper, pMOSFETs featuring atomic layer deposition (ALD) tungsten (W) using SiH4 and B2H6 precursors in 22 nm node CMOS technology were investigated. It is found that, in terms of threshold voltage, driving capability, carrier mobility, and the control of short-channel effects, the performance of devices featuring ALD W using SiH4 is superior to that of devices featuring ALD W using B2H6. This disparity in device performance results from different metal gate-induced strain from ALD W using SiH4 and B2H6 precursors, i.e. tensile stresses for SiH4 (similar to 2.4 GPa) and for B2H6 (similar to 0.9 GPa).

Place, publisher, year, edition, pages
SPRINGER, 2017
Keyword
ALD W, High-k and metal gate (HKMG), Nano-beam diffraction (NBD), Threshold voltage (V-t), Mobility
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-207672 (URN)10.1186/s11671-017-2080-2 (DOI)000400179500009 ()28449546 (PubMedID)2-s2.0-85018869577 (Scopus ID)
Note

QC 20170602

Available from: 2017-06-02 Created: 2017-06-02 Last updated: 2017-06-02Bibliographically approved
Yu, E., Ryu, S. W., Radamson, H. H. & Cho, S. (2017). Structural and Optical Characteristics of Epitaxially Grown SiGe on Si for Electronic and Photonic Device Applications. Journal of Nanoelectronics and Optoelectronics, 12(10), 1129-1133.
Open this publication in new window or tab >>Structural and Optical Characteristics of Epitaxially Grown SiGe on Si for Electronic and Photonic Device Applications
2017 (English)In: Journal of Nanoelectronics and Optoelectronics, ISSN 1555-130X, E-ISSN 1555-1318, Vol. 12, no 10, p. 1129-1133Article in journal (Refereed) Published
Abstract [en]

For higher device performances including low-power consumption and high-speed operation, functional materials in wide variety are actively studied. In particular, Si compatibility is regarded as one of the indispensable prerequisites owing to cost effectiveness and high maturity of Si platform and its process integration. SiGe is gaining much interest owing to Si compatibility, high carrier mobilities, and higher optical confinement capability compared with Si. In this work, SiGe layers have been epitaxially grown on Si substrate under different conditions and their structural and optical characteristics are analyzed in depth. Various analysis tools are used cooperatively, including high-resolution transmission electron microscopy (HR-TEM), dynamic secondary ion mass spectroscopy (SIMS), X-ray diffraction spectroscopy (XRD), and long-wavelength ellipsometer, in order to extract the thickness as the result of epitaxy condition, Ge fraction, interface status, lattice constant, and refractive index with extinction coefficient for setting up parameter database for electronic and photonic device applications.

Place, publisher, year, edition, pages
American Scientific Publishers, 2017
Keyword
Functional Material, Si Compatibility, SiGe, Carrier Mobility, Optical Confinement, HR-TEM, SIMS, XRD, Epitaxy, Ge Fraction
National Category
Nano Technology
Identifiers
urn:nbn:se:kth:diva-221893 (URN)10.1166/jno.2017.2109 (DOI)000419957000015 ()2-s2.0-85041114225 (Scopus ID)
Note

QC 20180131

Available from: 2018-01-31 Created: 2018-01-31 Last updated: 2018-02-06Bibliographically approved
Ebrahimi, P., Kolahdouz, M., Iraj, M., Ganjian, M., Aghababa, H., Asl-Soleimani, E. & Radamson, H. H. (2017). Systematic Optimization of Boron Diffusion for Solar Cell Emitters. Journal of Electronic Materials, 46(7), 4236-4241.
Open this publication in new window or tab >>Systematic Optimization of Boron Diffusion for Solar Cell Emitters
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2017 (English)In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 46, no 7, p. 4236-4241Article in journal (Refereed) Published
Abstract [en]

To achieve p-n junctions for n-type solar cells, we have studied BBr3 diffusion in an open tube furnace, varying parameters of the BBr3 diffusion process such as temperature, gas flows, and duration of individual process steps, i.e., predeposition and drive-in. Then, output parameters such as carrier lifetime, sheet resistance, and diffusion profile were measured and statistically analyzed to optimize the emitter characteristics. Statistical analysis (factorial design) was finally employed to systematically explore the effects of the set of input variables on the outputs. The effect of the interactions between inputs was also evaluated for each output, quantified using a two-level factorial method. Temperature and BBr3 flow were found to have the most significant effect on different outputs such as carrier lifetime, junction depth, sheet resistance, and final surface concentration.

Place, publisher, year, edition, pages
Springer, 2017
Keyword
Silicon solar cells, boron diffusion, sheet resistance, lifetime, junction depth
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-210460 (URN)10.1007/s11664-017-5364-5 (DOI)000403016800059 ()2-s2.0-85013751239 (Scopus ID)
Note

QC 20170706

Available from: 2017-07-06 Created: 2017-07-06 Last updated: 2017-07-06Bibliographically approved
Radamson, H. H., Zhang, Y., He, X., Cui, H., Li, J., Xiang, J., . . . Wang, G. (2017). The Challenges of Advanced CMOS Process from 2D to 3D. Applied Sciences, 7(10), Article ID 1047.
Open this publication in new window or tab >>The Challenges of Advanced CMOS Process from 2D to 3D
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2017 (English)In: Applied Sciences, E-ISSN 2076-3417, Vol. 7, no 10, article id 1047Article, review/survey (Refereed) Published
Abstract [en]

The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

Place, publisher, year, edition, pages
MDPI AG, 2017
Keyword
FinFETs, CMOS, device processing, integrated circuits
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:kth:diva-217946 (URN)10.3390/app7101047 (DOI)000414457800085 ()2-s2.0-85031506154 (Scopus ID)
Note

QC 20171121

Available from: 2017-11-21 Created: 2017-11-21 Last updated: 2018-01-13Bibliographically approved
Noroozi, M., Jayakumar, G., Zahmatkesh, K., Lu, J., Hultman, L., Mensi, M., . . . Radamson, H. H. (2017). Unprecedented thermoelectric power factor in SiGe nanowires field-effect transistors. ECS Journal of Solid State Science and Technology, 6(9), Q114-Q119.
Open this publication in new window or tab >>Unprecedented thermoelectric power factor in SiGe nanowires field-effect transistors
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2017 (English)In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 9, p. Q114-Q119Article in journal (Refereed) Published
Abstract [en]

In this work, a novel CMOS compatible process for Si-based materials has been presented to form SiGe nanowires (NWs) on SiGe On Insulator (SGOI) wafers with unprecedented thermoelectric (TE) power factor (PF). The TE properties of SiGe NWs were characterized in a back-gate configuration and a physical model was applied to explain the experimental data. The carrier transport in NWs was modified by biasing voltage to the gate at different temperatures. The PF of SiGe NWs was enhanced by a factor of >2 in comparison with bulk SiGe over the temperature range of 273 K to 450 K. This enhancement is mainly attributed to the energy filtering of carriers in SiGe NWs, which were introduced by imperfections and defects created during condensation process to form SiGe layer or in NWs during the processing of NWs.

Place, publisher, year, edition, pages
Electrochemical Society, 2017
National Category
Other Physics Topics
Identifiers
urn:nbn:se:kth:diva-218384 (URN)10.1149/2.0021710jss (DOI)000418363500019 ()2-s2.0-85033793013 (Scopus ID)
Funder
Swedish Foundation for Strategic Research , EM-011-0002Swedish Energy Agency, 43521-1Knut and Alice Wallenberg Foundation
Note

QC 20171128

Available from: 2017-11-28 Created: 2017-11-28 Last updated: 2018-01-08Bibliographically approved
Wang, G., Luo, J., Qin, C., Cui, H., Liu, J., Jia, K., . . . Radamson, H. H. (2016). Integration of selective epitaxial growth of SiGe/Ge layers in 14nm node FinFETs. In: ECS Transactions: . Paper presented at Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016 (pp. 273-279). Electrochemical Society Inc. (8).
Open this publication in new window or tab >>Integration of selective epitaxial growth of SiGe/Ge layers in 14nm node FinFETs
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2016 (English)In: ECS Transactions, Electrochemical Society Inc. , 2016, no 8, p. 273-279Conference paper, Published paper (Refereed)
Abstract [en]

In this study, the process integration of SiGe selective epitaxy on source/drain and SiGe/Ge bilayers selectively epitaxy on replacement Si channel regions for 14 nm node FinFETs has been presented. The epi-quality, layer profile and strain amount of the selectively grown SiGe and Ge layers were also investigated by means of various characterization tools. A series of prebaking experiments were performed for different temperatures in order to in-situ clean the Si fins prior to the SiGe S/D epitaxy. It was also found that a SiGe layer with graded Ge content was deposited as the strain relaxed buffer (SRB) layer in the channel trench prior to the Ge layer filling in the small trenches to make the void defect free.

Place, publisher, year, edition, pages
Electrochemical Society Inc., 2016
Keyword
Characterization, Epitaxial growth, Germanium, MOSFET devices, Channel region, Characterization tools, Process integration, Selective epitaxial growth, Selective epitaxy, Selectively epitaxy, Strain-relaxed buffer layers, Void defects, Silicon alloys
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-201973 (URN)10.1149/07508.0273ecst (DOI)2-s2.0-84991698876 (Scopus ID)9781607685395 (ISBN)
Conference
Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016
Note

QC 20170303

Available from: 2017-03-03 Created: 2017-03-03 Last updated: 2017-03-03Bibliographically approved
Kermaniha, M., Kolahdouz, M., Manavizadeh, N., Aghababa, H., Elahi, M., Iraj, M., . . . Radamson, H. H. (2016). Systematic optimization of phosphorous diffusion for solar cell application. Paper presented at Solar Asia International Conference, 2015, Savitribai Phule Pune Univ, Pune, INDIA. Journal of materials science. Materials in electronics, 27(12), 13086-13092.
Open this publication in new window or tab >>Systematic optimization of phosphorous diffusion for solar cell application
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2016 (English)In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 27, no 12, p. 13086-13092Article in journal (Refereed) Published
Abstract [en]

Fossil fuel storage is running low and scientists around the globe are involved in a big search for an optimized substitute. Photovoltaic is one of the most likely alternatives to solve this issue and replace the fossil fuels. Among all types of cells, silicon solar cells are the most economical ones to produce affordable energy. In this paper, a systematic study was done on the diffusion of phosphorous in multi-crystalline silicon during solar cell emitter formation. All parameters involved in the conversion of a multi-crystalline p-type silicon to a p-n junction were analyzed quantitatively. This systematic approach predicts the effect of inputs on the outputs which decreases the number of the trail runs. The analysis result indicate, that raising the diffusion temperature from 830 to 880 A degrees C decreases the sheet resistance by -100 Omega/sq, and increasing POCl3 flow from 300 to 500 SCCM has an effect of -21 Omega/sq.

Place, publisher, year, edition, pages
Springer-Verlag New York, 2016
National Category
Materials Engineering
Identifiers
urn:nbn:se:kth:diva-199526 (URN)10.1007/s10854-016-5452-y (DOI)000389231000103 ()2-s2.0-84982813104 (Scopus ID)
Conference
Solar Asia International Conference, 2015, Savitribai Phule Pune Univ, Pune, INDIA
Note

QC 20170116

Available from: 2017-01-16 Created: 2017-01-09 Last updated: 2017-11-29Bibliographically approved
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