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Abedin, Ahmad
Publications (5 of 5) Show all publications
Abedin, A., Zurauskaite, L., Asadollahi, A., Garidis, K., Jayakumar, G., Malm, B. G., . . . Östling, M. (2018). Germanium on Insulator Fabrication for Monolithic 3-D Integration. IEEE Journal of the Electron Devices Society, 6(1), 588-593
Open this publication in new window or tab >>Germanium on Insulator Fabrication for Monolithic 3-D Integration
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2018 (English)In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed) Published
Abstract [en]

A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018
Keywords
GOI, wafer bonding, selective etching, GOI MOSFET, 3D integration
National Category
Materials Chemistry
Identifiers
urn:nbn:se:kth:diva-231645 (URN)10.1109/JEDS.2018.2801335 (DOI)000435505000007 ()2-s2.0-85041650674 (Scopus ID)
Funder
Swedish Foundation for Strategic Research
Note

QC 20180904

Available from: 2018-09-04 Created: 2018-09-04 Last updated: 2018-10-19Bibliographically approved
Abedin, A., Zurauskaite, L., Asadollahi, A., Garidis, K., Jayakumar, G., Malm, B. G., . . . Östling, M. (2018). GOI fabrication for monolithic 3D integration. In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017: . Paper presented at 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Hyatt Regency San Francisco Airport Hotel Burlingame, United States, 16 October 2017 through 18 October 2017 (pp. 1-3). Institute of Electrical and Electronics Engineers (IEEE), 2018
Open this publication in new window or tab >>GOI fabrication for monolithic 3D integration
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2018 (English)In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper, Published paper (Refereed)
Abstract [en]

A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
3D Integration, GOI, GOI MOSFET, Selective Etching, Wafer Bonding
National Category
Other Engineering and Technologies
Identifiers
urn:nbn:se:kth:diva-230046 (URN)10.1109/S3S.2017.8309201 (DOI)2-s2.0-85047768082 (Scopus ID)9781538637654 (ISBN)
Conference
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Hyatt Regency San Francisco Airport Hotel Burlingame, United States, 16 October 2017 through 18 October 2017
Note

QC 20180611

Available from: 2018-06-11 Created: 2018-06-11 Last updated: 2018-06-11Bibliographically approved
Jablonka, L., Kubart, T., Primetzhofer, D., Abedin, A., Hellström, P.-E., Östling, M., . . . Zhang, Z. (2017). Formation of nickel germanides from Ni layers with thickness below 10 nm. Journal of Vacuum Science & Technology B, 35(2), Article ID 020602.
Open this publication in new window or tab >>Formation of nickel germanides from Ni layers with thickness below 10 nm
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2017 (English)In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 35, no 2, article id 020602Article in journal (Refereed) Published
Abstract [en]

The authors have studied the reaction between a Ge (100) substrate and thin layers of Ni ranging from 2 to 10 nm in thickness. The formation of metal-rich Ni5Ge3 was found to precede that of the monogermanide NiGe by means of real-time in situ x-ray diffraction during ramp-annealing and ex situ x-ray pole figure analyses for phase identification. The observed sequential growth of Ni5Ge3 and NiGe with such thin Ni layers is different from the previously reported simultaneous growth with thicker Ni layers. The phase transformation from Ni5Ge3 to NiGe was found to be nucleationcontrolled for Ni thicknesses < 5 nm, which is well supported by thermodynamic considerations. Specifically, the temperature for the NiGe formation increased with decreasing Ni (rather Ni5Ge3) thickness below 5 nm. In combination with sheet resistance measurement and microscopic surface inspection of samples annealed with a standard rapid thermal processing, the temperature range for achieving morphologically stable NiGe layers was identified for this standard annealing process. As expected, it was found to be strongly dependent on the initial Ni thickness.

Place, publisher, year, edition, pages
A V S AMER INST PHYSICS, 2017
National Category
Materials Chemistry
Identifiers
urn:nbn:se:kth:diva-205486 (URN)10.1116/1.4975152 (DOI)000397858500029 ()2-s2.0-85011265375 (Scopus ID)
Note

QC 20170523

Available from: 2017-05-23 Created: 2017-05-23 Last updated: 2017-11-29Bibliographically approved
Abedin, A., Asadollahi, A., Garidis, K., Hellström, P.-E. & Östling, M. (2016). Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density. In: ECS Transactions: . Paper presented at Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016 (pp. 615-621). Electrochemical Society (8)
Open this publication in new window or tab >>Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density
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2016 (English)In: ECS Transactions, Electrochemical Society, 2016, no 8, p. 615-621Conference paper, Published paper (Refereed)
Abstract [en]

Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

Place, publisher, year, edition, pages
Electrochemical Society, 2016
Keywords
Chemical vapor deposition, Silicon, Silicon alloys, Strain relaxation, Surface defects, Surface roughness, Surface topography, Temperature, Defects density, Low-dislocation density, Low-temperature grown, Mobility enhancement, Reduced pressure chemical vapor deposition, Strain relaxed buffers, Strain-relaxed, Threading dislocation densities, Germanium
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-201995 (URN)10.1149/07508.0615ecst (DOI)2-s2.0-84991585471 (Scopus ID)9781607685395 (ISBN)
Conference
Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016
Note

QC 20170224

Available from: 2017-02-24 Created: 2017-02-24 Last updated: 2018-01-15Bibliographically approved
Abedin, A., Zurauskaite, L. & Asadollahi, A. GOI fabrication for Monolithic 3D integration.
Open this publication in new window or tab >>GOI fabrication for Monolithic 3D integration
(English)In: Article in journal (Other academic) Submitted
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-221093 (URN)
Note

QC 20180115

Available from: 2018-01-12 Created: 2018-01-12 Last updated: 2018-01-15Bibliographically approved
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