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Ngo, Kalle
Publications (2 of 2) Show all publications
Kyriakakis, E., Ngo, K. & Öberg, J. (2017). Implementation of a Fault-Tolerant, Globally-Asynchronous-Locally-Synchronous, Inter-Chip NoC Communication Bridge on FPGAs. In: Nurmi, J Vesterbacka, M Wikner, JJ Alvandpour, A NielsenLonn, M Nielsen, IR (Ed.), 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC). Paper presented at 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS). IEEE
Open this publication in new window or tab >>Implementation of a Fault-Tolerant, Globally-Asynchronous-Locally-Synchronous, Inter-Chip NoC Communication Bridge on FPGAs
2017 (English)In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC) / [ed] Nurmi, J Vesterbacka, M Wikner, JJ Alvandpour, A NielsenLonn, M Nielsen, IR, IEEE , 2017Conference paper, Published paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) architectures were introduced to help mitigate the bottleneck and scalability issues faced by the traditional bus interconnect in Multi-Processor System-On Chip (MPSoC). Nowadays, many embedded systems host a significant number of micro-controllers and processors (i.e. vehicles, airplanes, satellites, etc.) and as this number continues to increase, traditional bus solutions will start to fail on those platforms as well. NoCs not only offer a scalable solution for MPSoC interconnects but they can also provide a uniform platform of communication to embedded systems with multiple off-chip, often heterogeneous, processors. This leads to the need for investigation on inter-chip communication bridges suitable for transmitting flits/packets across chips and possibly across clock domains. This paper investigates an inter-chip communication link, of an MPSoC NoC architecture which is extended with an off-chip, heterogeneous processor (node) and proposes a scalable, fault-tolerant, globally asynchronous locally synchronous bridge for inter-chip communication. The proposed bridge is implemented on a prototype board of the SEUD KTH experiment where it successfully enables the communication of a NoC distributed over two FPGAs. The inter-chip bridge is verified in-circuit achieving transfer speeds up to 24 MByte/s (approximate to 1.5 Mflit/s) and its ability to correct single bit errors is demonstrated in simulation.

Place, publisher, year, edition, pages
IEEE, 2017
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-223819 (URN)000425049100028 ()
Conference
2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS)
Note

QC 20180306

Available from: 2018-03-06 Created: 2018-03-06 Last updated: 2018-03-06Bibliographically approved
Kyriakakis, E., Ngo, K. & Öberg, J. (2017). Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller. In: Nurmi, J Vesterbacka, M Wikner, JJ Alvandpour, A NielsenLonn, M Nielsen, IR (Ed.), 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC). Paper presented at 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS). IEEE
Open this publication in new window or tab >>Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
2017 (English)In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC) / [ed] Nurmi, J Vesterbacka, M Wikner, JJ Alvandpour, A NielsenLonn, M Nielsen, IR, IEEE , 2017Conference paper, Published paper (Refereed)
Abstract [en]

From deep space missions to low-earth orbit satellites, the natural radiation of space proves to be a hostile environment for electronics. Memory elements in particular are highly susceptible to radiation charge that if latched can cause single-event upsets (SEU, bit-flips) which lead to data corruption and even mission critical failures. On Earth, SDRAM devices are widely used as a cost-effective, high performance storage elements in almost every computer system. However, their physical design makes them highly susceptible to SEUs. Thus, their usage in space application is limited and usually avoided, requiring the use of radiation hardened components which are generally a few generations older and often much more expensive than COTS. In this paper, an off-chip SEU/MBU mitigation mechanism is presented that aims to drastically reduce the probability of data corruption inside a commercial-off-the-shelf (COTS) synchronous dynamic random access memory (SDRAM) using a triple modular redundant (TMR) scheme for data and periodic scrubbing. The proposed mitigation technique is implemented in a novel controller that will be used by the single-event upset detector (SEUD) experiment aboard the KTH MInature STudent (MIST) satellite project.

Place, publisher, year, edition, pages
IEEE, 2017
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-223820 (URN)000425049100034 ()
Conference
2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS)
Note

QC 20180306

Available from: 2018-03-06 Created: 2018-03-06 Last updated: 2018-03-06Bibliographically approved
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