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Efficient Design-for-Test Approach for Networks-on-Chip
Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China.;Beijing Zhaoxin Elect Technol Co Ltd, Beijing 100084, Peoples R China..
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China..
Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China..
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2019 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 68, no 2, p. 198-213Article in journal (Refereed) Published
Abstract [en]

To achieve high reliability in on-chip networks, it is necessary to test the network continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the number of affected packets can be minimized. However, BISTcauses significant performance loss due to data dependencies. We propose EsyTest, a comprehensive test strategy with minimized influence on system performance. EsyTest tests the data path and the control path separately. The data path test starts periodically, but the actual test performs in the free time slots to avoid deactivating the router for testing. A reconfigurable router architecture and an adaptive fault-tolerant routing algorithm are proposed to guarantee the access to the processing core when the associated router is under test. During the whole test procedure of the network, all processing cores are accessible, and thus the system performance is maintained during the test. At the same time, EsyTest provides a full test coverage for the NoC and a better hardware compatibility comparing with the existing test strategies. Under the PARSEC benchmark and different test frequencies, the execution time increases less than 5 percent at the cost of 9.9 percent more area and 4.6 percent more power in comparison with the execution where no test procedure is applied.

Place, publisher, year, edition, pages
IEEE Computer Society Digital Library, 2019. Vol. 68, no 2, p. 198-213
Keywords [en]
Network-on-chip, non-blocking testing, reliability monitoring, reconfigurable router architecture, adaptive routing algorithm, built-in self-test
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-243937DOI: 10.1109/TC.2018.2865948ISI: 000456176200004Scopus ID: 2-s2.0-85051797924OAI: oai:DiVA.org:kth-243937DiVA, id: diva2:1294002
Note

QC 20190306

Available from: 2019-03-06 Created: 2019-03-06 Last updated: 2019-08-15Bibliographically approved

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Ebrahimi, Masoumeh

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