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Scalable Integration of High Sampling Rate Measurements in Deterministic Process-level Networks
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electric Power and Energy Systems.ORCID iD: 0000-0001-9073-0792
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electric Power and Energy Systems.ORCID iD: 0000-0002-6539-9265
KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Network and Systems Engineering.ORCID iD: 0000-0002-2764-8099
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electric Power and Energy Systems.ORCID iD: 0000-0003-3014-5609
(English)Manuscript (preprint) (Other academic)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-298948OAI: oai:DiVA.org:kth-298948DiVA, id: diva2:1581615
Note

QCR 20210802

Available from: 2021-07-22 Created: 2021-07-22 Last updated: 2022-06-25Bibliographically approved
In thesis
1. Distributed Signal Processing in Digital Substations: Integrating High Sampling Rate Measurements at the Process-Level
Open this publication in new window or tab >>Distributed Signal Processing in Digital Substations: Integrating High Sampling Rate Measurements at the Process-Level
2021 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Future power systems will be dominated by power electronic (PE) converter connected generation. This trend is primarily driven by the increasing penetration of wind power as well as the increasing integration of photovoltaic (PV) based generation. In general, these PE converter connected generation sources are expected to change the dynamic behavior of power systems. In particular, conventional phasor-based protection systems may be challenged by the reduced inertia and reduced short-circuit power, due respectively to non-synchronous generation and limited short-circuit power of PE converters.

Therefore, it has been proposed to utilize time-domain protection principles, which are more sensitive and operate faster than phasor-based protection functions. For instance, travelling-wave (TW) based differential protection analyses the magnitude, polarity and arrival time of the fault generated TWs when they reach the line terminals. This type of protection functions requires high sampling rates in the megahertz range and is characterized by fast cycle times. Today’s modern substations have digital secondary systems consisting of process-level networks and highly functionally integrated protection Intelligent Electronic Devices (IEDs). The integration of high sampling rate protection applications in digital substations is challenging, since they increase significantly the communication load on process-level networks as well as the computational load on highly functionally integrated IEDs and centralized protection platforms.

This thesis aims to test the hypothesis that a distributed signal processing architecture can provide a scalable integration of high sampling rate protection applications in digital substations without increasing vastly the communication load on process-level networks and computational load on highly functionally integrated protection IEDs. Therefore, the thesis proposes that the most computation- and communication-demanding signal extraction tasks of time-domain protection functions be allocated to a process-level device, termed Distributed Signal Processing Units (DSPU). Moreover, suitable data models for the protection signal features are derived based on the IEC 61850 modelling approach as well as their mapping to IEC standard compliant communication protocols is discussed. In addition, the results show that the communication load may be reduced significantly by the proposed distributed signal processing architecture, and also that an increased number of DSPUs can be connected to the same process-level network. Furthermore, as part of this thesis, a detailed design of the DSPU is developed, which has been optimized with respect to the processing delay and the computational costs. Finally, the proposed substation architecture is verified through electromagnetic transient (EMT) simulations.

Place, publisher, year, edition, pages
Stockholm, Sweden: KTH Royal Institute of Technology, 2021. p. 63
Series
TRITA-EECS-AVL ; 2021:53
Keywords
Communication networks, digital signal processing, digital substation, field-programmable gate array, filter design, IEC 61850, IEC 61869, power system protection, substation automation
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-300420 (URN)978-91-7873-944-8 (ISBN)
Public defence
2021-10-04, Kollegiesalen Zoom: https://kth-se.zoom.us/j/61033307653?pwd=ZFc0anNrWi8yamVYZzdpK1p2NzY3UT09, Brinellvägen 8, Stockholm, 10:00 (English)
Opponent
Supervisors
Note

QC 20210831

Available from: 2021-08-31 Created: 2021-08-30 Last updated: 2022-06-25Bibliographically approved

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Hohn, FabianZanuso, GiovanniFodor, ViktóriaNordström, Lars

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