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FPGA-Based HPC for Associative Memory System
Fudan Univ, Shanghai, Peoples R China..
Univ Turku, Turku, Finland..
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0003-2396-3590
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0002-5697-4272
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2024 (English)In: 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024, Institute of Electrical and Electronics Engineers (IEEE) , 2024, p. 52-57Conference paper, Published paper (Refereed)
Abstract [en]

Associative memory plays a crucial role in the cognitive capabilities of the human brain. The Bayesian Confidence Propagation Neural Network (BCPNN) is a cortex model capable of emulating brain-like cognitive capabilities, particularly associative memory. However, the existing GPU-based approach for BCPNN simulations faces challenges in terms of time overhead and power efficiency. In this paper, we propose a novel FPGA-based high performance computing (HPC) design for the BCPNN-based associative memory system. Our design endeavors to maximize the spatial and timing utilization of FPGA while adhering to the constraints of the available hardware resources. By incorporating optimization techniques including shared parallel computing units, hybrid-precision computing for a hybrid update mechanism, and the globally asynchronous and locally synchronous (GALS) strategy, we achieve a maximum network size of 150x10 and a peak working frequency of 100 MHz for the BCPNN-based associative memory system on the Xilinx Alveo U200 Card. The tradeoff between performance and hardware overhead of the design is explored and evaluated. Compared with the GPU counterpart, the FPGA-based implementation demonstrates significant improvements in both performance and energy efficiency, achieving a maximum latency reduction of 33.25x, and a power reduction of over 6.9x, all while maintaining the same network configuration.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2024. p. 52-57
Series
Asia and South Pacific Design Automation Conference Proceedings, ISSN 2153-6961
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-346310DOI: 10.1109/ASP-DAC58780.2024.10473880ISI: 001196002900009Scopus ID: 2-s2.0-85189308319OAI: oai:DiVA.org:kth-346310DiVA, id: diva2:1857362
Conference
29th Asia and South Pacific Design Automation Conference (ASP-DAC), JAN 22-25, 2024, BrainKorea Four 21, Incheon, SOUTH KOREA
Note

QC 20240513

Part of ISBN 979-8-3503-9354-5

Available from: 2024-05-13 Created: 2024-05-13 Last updated: 2024-05-13Bibliographically approved

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Yu, YangStathis, DimitriosHemani, AhmedLansner, Anders

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