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Automatic Parallelization of Embedded Software via Hierarchical Process Network Transformations
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0002-5897-4962
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0002-1277-3903
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0003-4859-3100
Ericsson AB, Stockholm, Sweden.ORCID iD: 0000-0003-1666-1316
2024 (English)In: 2024 forum on specification & design languages, FDL 2024, Institute of Electrical and Electronics Engineers (IEEE) , 2024, p. 37-45Conference paper, Published paper (Refereed)
Abstract [en]

To fully utilize multi-processors, new tools are required to manage software complexity. We present a novel technique that enables automating hierarchical process network transformations to derive optimized parallel applications. Designers leverage a library of process constructors and data-parallel algorithmic skeletons, utilizing the well-defined semantics of a restricted set of operators. This carefully chosen set addresses both temporal and spatial aspects of computation, enabling the automated identification of various parallel patterns. We utilize an augmented version of a meta-modeling framework grounded in system graphs and trait hierarchies to generate an intermediate representation (IR) of the system model to simplify automatic transformations and evaluations. Our augmentation allows for capturing skeletons and hierarchical networks. By meticulously selecting the underlying framework, we alleviate the need for tool integration in our design flow. We validate our approach through a proof-of-concept implementation, where our automated tool applied 193 transformations to fully parallelize an image processing application.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2024. p. 37-45
Series
International Forum on Design Languages, ISSN 1636-9874
Keywords [en]
embedded systems, software parallelization, process network transformation, design transformation
National Category
Computer Sciences Software Engineering
Identifiers
URN: urn:nbn:se:kth:diva-356025DOI: 10.1109/FDL63219.2024.10673845ISI: 001324887800005Scopus ID: 2-s2.0-85206251790OAI: oai:DiVA.org:kth-356025DiVA, id: diva2:1912018
Conference
27th Forum on Specification and Design Languages (FDL), SEP 04-06, 2024, KTH Royal Inst Technol, Stockholm, SWEDEN
Note

Part of ISBN 979-8-3315-0458-8, 979-8-3315-0457-1

QC 20241111

Available from: 2024-11-11 Created: 2024-11-11 Last updated: 2025-06-19Bibliographically approved

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fulltext(1161 kB)8 downloads
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Bahrami, FahimehJordao, RodolfoSander, IngoUngureanu, George

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CiteExportLink to record
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Citation style
  • apa
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Output format
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