Surge current capability of paralleled silicon carbide (SiC) metal-oxide-semiconductor-field-effect transistors (mosfets) operating in both first and third quadrants is required in various applications. The surge current distribution in paralleled SiC mosfets during third quadrant operation needs further investigations. This article, therefore, establishes a source-drain resistance model of SiC mosfets under different gate bias in surge current range, which reveals the current "competition mechanism" between the MOS-channel path and the body diode path under surge current conditions. It then investigates the influence of device parameters discrepancy on surge current distribution in paralleled SiC mosfets. It finds out that the discrepancy of body diode parameters has significant influences on surge current distribution under different gate biases, while the parameter discrepancy of MOS-channel has much smaller impact on surge current distribution, even with positive gate bias. The conclusions of this article are supported with simulation and experimental results.