Predicting bus contention effects on energy and performance in multi-processor SoCs 2011 (English)In: 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011, 2011, p. 1196-1199Conference paper, Published paper (Other academic)

Place, publisher, year, edition, pages

2011. p. 1196-1199

Keywords [en]

algorithmic specification;bus contention effect prediction;gate-level estimation;multiprocessor SoC;microprocessor chips;system-on-chip;

National Category

Embedded Systems

Identifiers

URN: urn:nbn:se:kth:diva-49325ISI: 000410278900229Scopus ID: 2-s2.0-79957550145OAI: oai:DiVA.org:kth-49325DiVA, id: diva2:459515

Conference

Design, Automation and Test in Europe, DATE. Grenoble. 14 March 2011 - 18 March 2011

Note

QC 20111129

Available from: 2011-11-25 Created: 2011-11-25 Last updated: 2022-06-24Bibliographically approved

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Sander, IngoHemani, Ahmed

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