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Impact of etch factor on characteristic impedance, crosstalk and board density
Luleå Tekniska Universitet .ORCID iD: 0000-0002-4897-5603
KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electric Power and Energy Systems.ORCID iD: 0000-0003-0933-6945
Luleå Tekniska Universitet .
Luleå Tekniska Universitet .ORCID iD: 0000-0002-4133-3317
2012 (English)In: International Symposium on Microelectronics, no 1, p. 312-317Article in journal (Refereed) Published
Abstract [en]

Signal integrity becomes more important when the length of the Printed Wiring Board (PWB) traces surpasses λ/10 where λ denotes the wavelength. For fast digital communication purpose and low energy consumption in CMOS technology, faster rise time of the clock which means higher harmonic frequency, has always been preferable. In this case, the importance of considering signal integrity gets a higher priority as issues such reections and crosstalk between adjacent traces cannot be omitted, especially in dense High Density Interconnect (HDI) boards. Several factors control the effect of reections and the crosstalk such as the shape and dimension of the traces, the isolator characteristics which is inserted between the trace and the ground plane, the nearness and the geometry of the nearby conductors. In other words, these factors control the characteristic impedance of the traces and the mutual inductances and capacitances between the adjacent traces. Although these factors have been taken into account during the design phase for good signal integrity, the manufacturing process, which differs from vendor to vendor, has a great impact on the above factors. PWB manufacturing process may result in many different variations, which involve the dielectric constant, the thickness of the insulator, the trace width and the copper foil thickness. In addition to these variations, the etching quality that falls mainly in three different categories of trapezoidal trace form. In this paper we present the effect of three different etching shapes on the characteristic impedance. Moreover, it is concluded that one could gain space which can be used for shrinking the electronics and/or saving the raw material when trading the characteristic impedance error for space. Similar method is followed to investigate the crosstalk reduction between two adjacent microstriplines when tolerating the error in the characteristic impedance. This procedure can only be applied when a 90° etch angle process is feasible.

Place, publisher, year, edition, pages
2012. no 1, p. 312-317
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
URN: urn:nbn:se:kth:diva-222474DOI: 10.4071/isom-2012-TP24Scopus ID: 2-s2.0-84876914789OAI: oai:DiVA.org:kth-222474DiVA, id: diva2:1181762
Note

QC 20180212

Available from: 2018-02-09 Created: 2018-02-09 Last updated: 2018-02-12Bibliographically approved

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Risseh, Arash

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