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Distributed Two-stage Network Topology Processor for HVDC Grid Operation
KTH, Skolan för elektroteknik och datavetenskap (EECS), Elkraftteknik.ORCID-id: 0000-0003-3946-7655
KTH, Skolan för elektroteknik och datavetenskap (EECS), Elkraftteknik.
KTH, Skolan för elektroteknik och datavetenskap (EECS), Elkraftteknik.
KTH, Skolan för elektroteknik och datavetenskap (EECS), Elkraftteknik.ORCID-id: 0000-0003-3014-5609
2017 (engelsk)Inngår i: 2017 IEEE POWER & ENERGY SOCIETY GENERAL MEETING, IEEE , 2017Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

This paper presents the results of an analysis of distributed two-stage coordination of network topology processor for HVDC grids. In the first stage of the two-stage processor, the substation topology is analyzed locally using an automated graph based algorithm. Thereafter, a distributed algorithm is proposed to used the neighboring information to realize the grid connectivity. For distributed islanding detection, the connectivity problem is formulated as a set of linear equations and solved iteratively using successive-over-relaxation method. The performance of the proposed methods versus conventional one-stage method has been tested in an islandinv, scenario for a 5-terminal HVDC grid.

sted, utgiver, år, opplag, sider
IEEE , 2017.
Serie
IEEE Power and Energy Society General Meeting PESGM, ISSN 1944-9925
Emneord [en]
distributed coordination, HVDC grid, topology processor
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-228181DOI: 10.1109/PESGM.2017.8274088ISI: 000426921801072Scopus ID: 2-s2.0-85046345247ISBN: 978-1-5386-2212-4 (tryckt)OAI: oai:DiVA.org:kth-228181DiVA, id: diva2:1208988
Konferanse
2017 IEEE Power & Energy Society General Meeting, JUL 16-20, 2017, Chicago, IL
Merknad

QC 20180521

Tilgjengelig fra: 2018-05-21 Laget: 2018-05-21 Sist oppdatert: 2018-11-19bibliografisk kontrollert

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Forlagets fulltekstScopushttp://www.pes-gm.org/2017/

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