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Low-parasitic-capacitance self-aligned 4H-SiC nMOSFETs for harsh environment electronics
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2018 (engelsk)Inngår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 924, s. 971-974Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

Low-parasitic-capacitance 4H-SiC nMOSFETs using a novel self-aligned process were suggested and demonstrated. In these nMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain, drain-source capacitance) were investigated and low parasitic capacitance was achieved by the self-aligned structure

sted, utgiver, år, opplag, sider
Trans Tech Publications, 2018. Vol. 924, s. 971-974
Emneord [en]
Harsh environment electronics, Self-aligned Process, SiC nMOSFET, Capacitance, Electric breakdown, MOSFET devices, Silicon carbide, Device characteristics, Drain sources, Harsh environment, Low-parasitic, NMOSFET, Parasitic capacitance, Self aligned process, Self aligned structure, Fluorine compounds
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Identifikatorer
URN: urn:nbn:se:kth:diva-236430DOI: 10.4028/www.scientific.net/MSF.924.971Scopus ID: 2-s2.0-85049049901ISBN: 9783035711455 (tryckt)OAI: oai:DiVA.org:kth-236430DiVA, id: diva2:1258777
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QC 20181025

Tilgjengelig fra: 2018-10-25 Laget: 2018-10-25 Sist oppdatert: 2018-10-25bibliografisk kontrollert

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Östling, MikaelZetterling, Carl-Mikael

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