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Study and implementation of a secure random number generator for DSRC devices
KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar.
2018 (engelsk)Inngår i: 2017 9th IEEE-GCC Conference and Exhibition, GCCCE 2017, Institute of Electrical and Electronics Engineers Inc. , 2018Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

This work presents an algorithm to select a low-cost modulus for the implementation of Blum Blum Shub pseudorandom number generator in an FPGA device. Additionally, it elaborates a low-latency architecture for the BBS algorithm suitable for the security service of the IEEE 1609.2 standard. The architecture uses diminished-1 arithmetic and is log2($N$) faster than previously reported implementation using Montgomery multiplier. The architecture is able to implement 224-bit and 256-bit BBS sequences. Synthesis results show that the latencies for the 224-bit and 256-bit BBS are, respectively, 1.12μs and 1.28μs.

sted, utgiver, år, opplag, sider
Institute of Electrical and Electronics Engineers Inc. , 2018.
Emneord [en]
Digital arithmetic, Elliptic curves, Field programmable gate array, Random number generator, Vehicle ad hoc networks, Field programmable gate arrays (FPGA), Network architecture, Number theory, Vehicular ad hoc networks, Elliptic curve, FPGA devices, Low latency, Montgomery multipliers, Pseudo random number generators, Random number generators, Security services, Vehicle ad-hoc networks, Random number generation
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Identifikatorer
URN: urn:nbn:se:kth:diva-238000DOI: 10.1109/IEEEGCC.2017.8448202ISI: 000468867400048Scopus ID: 2-s2.0-85053936883ISBN: 9781538627563 (tryckt)OAI: oai:DiVA.org:kth-238000DiVA, id: diva2:1279059
Konferanse
9th IEEE-GCC Conference and Exhibition, GCCCE 2017, 8 May 2017 through 11 May 2017
Merknad

QC 20190115

Tilgjengelig fra: 2019-01-15 Laget: 2019-01-15 Sist oppdatert: 2019-08-13bibliografisk kontrollert

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Totalt: 180 treff
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