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HLS based DSP optimization with ASIC RTL libraries
Tampere University of Technology, Signal Processing Laboratory.
KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.ORCID-id: 0000-0002-8072-1742
KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.ORCID-id: 0000-0003-0565-9376
KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
1994 (engelsk)Inngår i:  , 1994, s. 218-225Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

In this paper we show how the High Level Synthesis (HLS) tool can efficiently be used for DSP ASIC development. The performance of general HLS tool is improved with simple transformations and code optimizations, and a direct mapping to technology optimized parameterizable ASIC Register Transfer Level (RTL) library. The library mapping contains three phases: a structure recognition, an architecture selection and a parameter optimization. As an optimization framework SYNT, Synopsys and Matlab design environments are integrated. Lsi10k and Xilinx 4000 series are used as target technologies to demonstrate the performance of the approach

sted, utgiver, år, opplag, sider
1994. s. 218-225
Emneord [en]
ASIC RTL libraries; ASIC development; DSP optimization; Lsi10k series; Matlab; SYNT; Synopsys; Xilinx 4000 series; architecture selection; code optimizations; design environments; high level synthesis; parameter optimization; register transfer level; structure recognition; high level synthesis;
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Identifikatorer
URN: urn:nbn:se:kth:diva-73083DOI: 10.1109/VLSISP.1994.574746OAI: oai:DiVA.org:kth-73083DiVA, id: diva2:488516
Konferanse
VLSI Signal Processing, VII, 1994., [Workshop on]
Merknad
NR 20140805Tilgjengelig fra: 2012-02-01 Laget: 2012-02-01 Sist oppdatert: 2012-02-17bibliografisk kontrollert

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