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Exploring ASIC Design Space at System Level with a Neural Network Estimator
KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.ORCID-id: 0000-0002-8072-1742
KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.ORCID-id: 0000-0003-0565-9376
Vise andre og tillknytning
1994 (engelsk)Inngår i: Proc. of IEEE ASIC-conference, 1994, 1994Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Estimators are critical tools in doing architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows to describe arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and we present results of the first experiments made with realistic design examples.

sted, utgiver, år, opplag, sider
1994.
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-89937OAI: oai:DiVA.org:kth-89937DiVA, id: diva2:503980
Konferanse
7th Annual IEEE international ASIC-conference, ASIC'94
Merknad

QC 20121121

Tilgjengelig fra: 2012-02-17 Laget: 2012-02-17 Sist oppdatert: 2012-11-21bibliografisk kontrollert

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Öberg, JohnnyHemani, Ahmed

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Ellervee, PeeterJantsch, AxelÖberg, JohnnyHemani, AhmedTenhunen, Hannu
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