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Area-efficient high-coverage LBIST
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.ORCID-id: 0000-0001-7382-9408
2014 (engelsk)Inngår i: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 38, nr 5, s. 368-374Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

Logic Built-In Self Test (LBIST) is a popular technique for applications requiring in-field testing of digital circuits. LBIST incorporates test generation and response-capture on-chip. It requires no interaction with a large, expensive tester. LBIST offers test time reduction due to at-speed test pattern application, makes possible test data re-usability at many levels, and enables test-ready IP. However, the traditional pseudo-random pattern-based LBIST often has a low test coverage. This paper presents a new method for on-chip generation of deterministic test patterns based on registers with non-linear update. Our experimental results on 7 real designs show that the presented approach can achieve a higher stuck-at coverage than the test point insertion with less area overhead. We also show that registers with non-linear update are asymptotically smaller than memories required to store the same test patterns in a compressed form.

sted, utgiver, år, opplag, sider
2014. Vol. 38, nr 5, s. 368-374
Emneord [en]
LBIST, LFSR, Top-off test patterns, In-field testing, Test compression
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-150537DOI: 10.1016/j.micpro.2014.05.002ISI: 000340300900002Scopus ID: 2-s2.0-84901824272OAI: oai:DiVA.org:kth-150537DiVA, id: diva2:744382
Merknad

QC 20140908

Tilgjengelig fra: 2014-09-08 Laget: 2014-09-05 Sist oppdatert: 2017-12-05bibliografisk kontrollert
Inngår i avhandling
1. Improvements in High-Coverage and Low-Power LBIST
Åpne denne publikasjonen i ny fane eller vindu >>Improvements in High-Coverage and Low-Power LBIST
2015 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

Testing cost is one of the major contributors to the manufacturing cost of integrated circuits. Logic Built-In Self Test (LBIST) offers test cost reduction in terms of using smaller and cheaper ATE, test data volume reduction due to on-chip test pattern generation, test time reduction due to at-speed test pattern application. However, it is difficult to reach a sufficient test coverage with affordable area overhead using LBIST. Also, excessive power dissipation during test due to the random nature of LBIST patterns causes yield-decreasing problems such as IR-drop and overheating.

In this dissertation, we present techniques and algorithms addressing these problems.

In order to increase test coverage of LBIST, we propose to use on-chip circuitry to store and generate the "top-off" deterministic test patterns. First, we study the synthesis of Registers with Non-Linear Update (RNLUs) as on-chip sequence generators. We present algorithms constructing RNLUs which generate completely and incompletely specified sequences. Then, we evaluate the effectiveness of RNLUs generating deterministic test patterns on-chip. Our experimental results show that we are able to achieve higher test coverage with less area overhead compared to test point insertion. Finally, we investigate the possibilities of integrating the presented on-chip deterministic test pattern generator with existing Design-For-Testability (DFT) techniques with a case study.

The problem of excessive test power dissipation is addressed with a scan partitioning algorithm which reduces capture power for delay-fault LBIST. The traditional S-graph model for scan partitioning does not quantify the dependency between scan cells. We present an algorithm using a novel weighted S-graph model in which the weights are scan cell dependencies determined by signal probability analysis. Our experimental results show that, on average, the presented method reduces average capture power by 50% and peak capture power by 39% with less than 2% drop in the transition fault coverage. By comparing the proposed algorithm to the original scan partitioning, we show that the proposed method is able to achieve higher capture power reduction with less fault coverage drop.

sted, utgiver, år, opplag, sider
Stockholm: KTH Royal Institute of Technology, 2015. s. xi, 84
Serie
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 15:05
HSV kategori
Identifikatorer
urn:nbn:se:kth:diva-165463 (URN)978-91-7595-538-4 (ISBN)
Disputas
2015-06-01, Sal A, Isafjordsgatan 26, Kista, 13:00 (engelsk)
Opponent
Veileder
Merknad

QC 20150508

Tilgjengelig fra: 2015-05-08 Laget: 2015-04-28 Sist oppdatert: 2018-01-11bibliografisk kontrollert

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