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Integrated logic synthesis using simulated annealing
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.ORCID-id: 0000-0001-7382-9408
Cadence Berkeley Labs, Berkeley, CA 94704, United States .
2011 (engelsk)Inngår i: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2011, 407-410 s.Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Conventional logic synthesis flows are composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions. In this paper, we present a method for integrating the three synthesis phases using an annealing algorithm as optimization framework. The annealing-based search is driven by a complex objective function, combining both technology independent as well as technology dependent optimization criteria. Our experimental results shown that, on average, the presented approach can improve the area and delay of circuits optimized with script rugged of SIS by 11.2% and 32.5% respectively.

sted, utgiver, år, opplag, sider
2011. 407-410 s.
Serie
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Emneord [en]
Rule-based optimization, Simulated annealing, Annealing algorithm, Fundamental problem, Logic restructuring, Logic structures, Logic synthesis, Objective functions, Optimization algorithms, Optimization criteria, Optimization framework, Technology independent, Technology mapping, Technology parameters, Algorithms, Delay circuits, Lakes, Technology
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-151214DOI: 10.1145/1973009.1973095Scopus ID: 2-s2.0-79957755779ISBN: 9781450306676 (tryckt)OAI: oai:DiVA.org:kth-151214DiVA: diva2:748347
Konferanse
21st Great Lakes Symposium on VLSI, GLSVLSI 2011, 2 May 2011 through 4 May 2011, Lausanne
Merknad

QC 20140919

Tilgjengelig fra: 2014-09-19 Laget: 2014-09-15 Sist oppdatert: 2014-09-19bibliografisk kontrollert

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