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High throughput architecture for high performance NoC
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. Ohio State University, Columbus, United States . (RaMSiS Group)
2009 (engelsk)Inngår i: ISCAS: 2009 IEEE International Symposium on Circuits and Systems, IEEE , 2009, s. 2241-2244Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.

sted, utgiver, år, opplag, sider
IEEE , 2009. s. 2241-2244
Serie
Proceedings - IEEE International Symposium on Circuits and Systems, ISSN 0271-4310
Emneord [en]
BFT, Latency, NoC, Throughput
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-153565DOI: 10.1109/ISCAS.2009.5118244ISI: 000275929801247Scopus ID: 2-s2.0-70350165397ISBN: 978-142443828-0 (tryckt)OAI: oai:DiVA.org:kth-153565DiVA, id: diva2:754953
Konferanse
2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, 24 May 2009 through 27 May 2009, Taipei, Taiwan
Merknad

QC 20141013

Tilgjengelig fra: 2014-10-13 Laget: 2014-10-06 Sist oppdatert: 2018-01-11bibliografisk kontrollert

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