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SysML Methodology for HIL Implementation of PV Models
Universidad de Los Andes, Colombia; Univ. de Toulouse, Univ. Paul Sabatier, France.ORCID-id: 0000-0001-5417-5939
KTH, Skolan för elektro- och systemteknik (EES), Elkraftteknik.ORCID-id: 0000-0003-2128-2425
Vise andre og tillknytning
2015 (engelsk)Inngår i: 2015 17TH EUROPEAN CONFERENCE ON POWER ELECTRONICS AND APPLICATIONS (EPE'15 ECCE-EUROPE), IEEE , 2015Konferansepaper, Publicerat paper (Fagfellevurdert)
Resurstyp
Text
Abstract [en]

This paper describes a methodology for implementing in FPGA models of photovoltaic panels for Hardware-in-the-Loop (HIL) and real-time simulations. The proposed methodology integrates numerical solutions, SysML diagrams and Petri nets for structural design and formal validation. In this study, photovoltaic cells have been modeled using the single diode circuit. The photovoltaic panel model is solved by the Newton-Raphson method, and the Lagrange remainder is employed to limit the iteration number. Results show suitable accuracy and performance of the proposed methodology.

sted, utgiver, år, opplag, sider
IEEE , 2015.
Serie
European Conference on Power Electronics and Applications, ISSN 2325-0313
Emneord [en]
Photovoltaic panel, Hardware-in-the-Loop, FPGA, SysML, Petri net
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-189409DOI: 10.1109/EPE.2015.7309196ISI: 000377101801039Scopus ID: 2-s2.0-84965074519ISBN: 9789075815238 (tryckt)OAI: oai:DiVA.org:kth-189409DiVA, id: diva2:947186
Konferanse
17th European Conference on Power Electronics and Applications (EPE ECCE-Europe), SEP 08-10, 2015, Geneva, SWITZERLAND
Merknad

QC 20160707

Tilgjengelig fra: 2016-07-07 Laget: 2016-07-04 Sist oppdatert: 2024-03-18bibliografisk kontrollert

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Gutierrez, A.Chamorro, H.R.

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