Ändra sökning
RefereraExporteraLänk till posten
Permanent länk

Direktlänk
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annat format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annat språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
TDM virtual-circuit configuration for network-on-chip
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.ORCID-id: 0000-0003-0061-3475
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
2008 (Engelska)Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 16, nr 8, s. 1021-1034Artikel i tidskrift (Refereegranskat) Published
Abstract [en]

In network-on-chip (NoC), time-division-multiplexing (TDM) virtual circuits (VCs) have been proposed to satisfy the quality-of-service requirements of applications. TDM VC is a connection-oriented communication service by which two or more connections take turns to share buffers and link bandwidth using dedicated time slots. In the paper, we first give a formulation of the multinode VC configuration problem for arbitrary NoC topologies. A multinode VC allows multiple source and destination nodes on it. Then we address the two problems of path selection and slot allocation for TDM VC configuration. For the path selection, we use a backtracking algorithm to explore the path diversity, constructively searching the solution space. In the slot allocation phase, overlapped VCs must be configured such that no conflict occurs and their bandwidth requirements are satisfied. We define the concept of a logical network (LN) as an infinite set of associated (time slot, buffer) pairs with respect to a buffer on a given VC. Based on this concept, we develop and prove theorems that constitute sufficient and necessary conditions to establish conflict-free VCs. They are applicable for networks where all nodes operate with the same clock frequency but allowing different phases. Using these theorems, slot allocation for VCs is a procedure of assigning VCs to different LNs. TDM VC configuration can thus be predictable and correct-by-construction. Our experiments on synthetic and real applications validate the effectiveness and efficiency of our approach.

Ort, förlag, år, upplaga, sidor
2008. Vol. 16, nr 8, s. 1021-1034
Nyckelord [en]
Logical network, network-on-chip (NoC), quality of service (QoS), time division multiplexing (TDM), virtual circuit
Nationell ämneskategori
Annan elektroteknik och elektronik
Identifikatorer
URN: urn:nbn:se:kth:diva-13058DOI: 10.1109/TVLSI.2008.2000673ISI: 000257987400008Scopus ID: 2-s2.0-48349101315OAI: oai:DiVA.org:kth-13058DiVA, id: diva2:320455
Anmärkning
QC 20100525Tillgänglig från: 2010-05-25 Skapad: 2010-05-25 Senast uppdaterad: 2017-12-12Bibliografiskt granskad
Ingår i avhandling
1. Design and Analysis of On-Chip Communication for Network-on-Chip Platforms
Öppna denna publikation i ny flik eller fönster >>Design and Analysis of On-Chip Communication for Network-on-Chip Platforms
2007 (Engelska)Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
Abstract [en]

Due to the interplay between increasing chip capacity and complex applications, System-on-Chip (SoC) development is confronted by severe challenges, such as managing deep submicron effects, scaling communication architectures and bridging the productivity gap. Network-on-Chip (NoC) has been a rapidly developed concept in recent years to tackle the crisis with focus on network-based communication. NoC problems spread in the whole SoC spectrum ranging from specification, design, implementation to validation, from design methodology to tool support. In the thesis, we formulate and address problems in three key NoC areas, namely, on-chip network architectures, NoC network performance analysis, and NoC communication refinement.

Quality and cost are major constraints for micro-electronic products, particularly, in high-volume application domains. We have developed a number of techniques to facilitate the design of systems with low area, high and predictable performance. From flit admission and ejection perspective, we investigate the area optimization for a classical wormhole architecture. The proposals are simple but effective. Not only offering unicast services, on-chip networks should also provide effective support for multicast. We suggest a connection-oriented multicasting protocol which can dynamically establish multicast groups with quality-of-service awareness. Based on the concept of a logical network, we develop theorems to guide the construction of contention-free virtual circuits, and employ a back-tracking algorithm to systematically search for feasible solutions.

Network performance analysis plays a central role in the design of NoC communication architectures. Within a layered NoC simulation framework, we develop and integrate traffic generation methods in order to simulate network performance and evaluate network architectures. Using these methods, traffic patterns may be adjusted with locality parameters and be configured per pair of tasks. We propose also an algorithm-based analysis method to estimate whether a wormhole-switched network can satisfy the timing constraints of real-time messages. This method is built on traffic assumptions and based on a contention tree model that captures direct and indirect network contentions and concurrent link usage.

In addition to NoC platform design, application design targeting such a platform is an open issue. Following the trends in SoC design, we use an abstract and formal specification as a starting point in our design flow. Based on the synchronous model of computation, we propose a top-down communication refinement approach. This approach decouples the tight global synchronization into process local synchronization, and utilizes synchronizers to achieve process synchronization consistency during refinement. Meanwhile, protocol refinement can be incorporated to satisfy design constraints such as reliability and throughput.

The thesis summarizes the major research results on the three topics.

Ort, förlag, år, upplaga, sidor
Stockholm: KTH, 2007. s. xvi, 109
Serie
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 2007:02
Nyckelord
On-Chip Communication, Network-on-Chip, System-on-Chip
Nationell ämneskategori
Annan elektroteknik och elektronik
Identifikatorer
urn:nbn:se:kth:diva-4290 (URN)978-91-7178-580-0 (ISBN)
Disputation
2007-03-15, D, KTH Forum, Isafördsgatan 39, Kista, 13:00 (Engelska)
Opponent
Handledare
Anmärkning
QC 20100525Tillgänglig från: 2007-02-28 Skapad: 2007-02-28 Senast uppdaterad: 2010-08-06Bibliografiskt granskad

Open Access i DiVA

Fulltext saknas i DiVA

Övriga länkar

Förlagets fulltextScopus

Personposter BETA

Lu, Zhonghai

Sök vidare i DiVA

Av författaren/redaktören
Lu, ZhonghaiJantsch, Axel
Av organisationen
Elektronik- och datorsystem, ECS
I samma tidskrift
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
Annan elektroteknik och elektronik

Sök vidare utanför DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetricpoäng

doi
urn-nbn
Totalt: 613 träffar
RefereraExporteraLänk till posten
Permanent länk

Direktlänk
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annat format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annat språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf