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Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.ORCID-id: 0000-0003-0568-0984
KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.ORCID-id: 0000-0001-6705-1660
Vise andre og tillknytning
2016 (engelsk)Inngår i: ECS Transactions, Electrochemical Society, 2016, nr 8, s. 615-621Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

sted, utgiver, år, opplag, sider
Electrochemical Society, 2016. nr 8, s. 615-621
Emneord [en]
Chemical vapor deposition, Silicon, Silicon alloys, Strain relaxation, Surface defects, Surface roughness, Surface topography, Temperature, Defects density, Low-dislocation density, Low-temperature grown, Mobility enhancement, Reduced pressure chemical vapor deposition, Strain relaxed buffers, Strain-relaxed, Threading dislocation densities, Germanium
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-201995DOI: 10.1149/07508.0615ecstScopus ID: 2-s2.0-84991585471ISBN: 9781607685395 (tryckt)OAI: oai:DiVA.org:kth-201995DiVA, id: diva2:1077049
Konferanse
Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016
Merknad

QC 20170224

Tilgjengelig fra: 2017-02-24 Laget: 2017-02-24 Sist oppdatert: 2018-01-15bibliografisk kontrollert
Inngår i avhandling
1. Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration
Åpne denne publikasjonen i ny fane eller vindu >>Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration
2018 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

The conventional 2D geometrical scaling of transistors is now facing many challenges in order to continue the performance enhancement while decreasing power consumption. The decrease in the device power consumption is related to the scaling of the power supply voltage (Vdd) and interconnects wiring length. In addition, monolithic three dimensional (M3D) integration in the form of vertically stacked devices, is a possible solution to increase the device density and reduce interconnect wiring length. Integrating strained germanium on insulator (sGeOI) pMOSFETs monolithically with strained silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs can increase the device performance and packing density. Low temperature processing (<550 ºC) is essential as interconnects and strained layers limit the thermal budget in M3D. This thesis presents an experimental investigation of the low temperature (<450 ºC) fabrication of group IV semiconductor-on-insulator substrates with the focus on sGeOI and sSiGeOI fabrication processes compatible with M3D.

  To this aim, direct bonding was used to transfer the relaxed and strained semiconductor layers. The void formation dependencies of the oxide thickness, the surface treatment of the oxide and the post annealing time were fully examined. Low temperature SiGe epitaxy was investigated with the emphasis on the fabrication of Si0.5Ge0.5 strain-relaxed buffers (SRBs), etch-stop layer, and the device layer in the SiGeOI and GeOI process schemes. Ge epitaxial growth on Si as thick SRBs and thin device layers was investigated. Thick (500 nm-3 µm) and thin (<30 nm) relaxed GeOI substrates were fabricated. The latter was fabricated by continuous epitaxial growth of a 3-µm Ge (SRB)/Si0.5Ge0.5 (etch stop)/Ge (device layer) stack on Si. The fabricated long channel Ge pFETs from these GeOI substrates exhibit well-behaved IV characteristics with an effective mobility of 160 cm2/Vs.

  The planarization of SiO2 and SiGe SRBs for the fabrication of the strained GeOI and SiGeOI were accomplished by chemical mechanical polishing (CMP). Low temperature processes (<450 ºC) were developed for compressively strained GeOI layers (ɛ ~ -1.75 %, < 20 nm), which are used for high mobility and low power devices. For the first time, tensile strained Si0.5Ge0.5 (ɛ ~ 2.5 %, < 20 nm) films were successfully fabricated and transferred onto patterned substrates for 3D integration.

sted, utgiver, år, opplag, sider
Kungliga Tekniska högskolan, 2018. s. 139
Serie
TRITA-EECS-AVL ; 2018:01
Emneord
monolithic three dimensional (M3D) integration, strained germanium on insulator (sGeOI) pMOSFETs, silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs, Si0.5Ge0.5 strain-relaxed buffer (SRB), direct bonding, chemical mechanical polishing (CMP), compressively strained GeOI, tensile strained Si0.5Ge0.5OI
HSV kategori
Identifikatorer
urn:nbn:se:kth:diva-221097 (URN)978-91-7729-658-4 (ISBN)
Disputas
2018-02-16, Ka-Sal C, Electrum, Kungliga Tekniska högskolan, Kistagången 16, Kista, Stockholm, 10:00 (engelsk)
Opponent
Veileder
Merknad

QC 20180115

Tilgjengelig fra: 2018-01-15 Laget: 2018-01-12 Sist oppdatert: 2018-01-19bibliografisk kontrollert

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