Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Parallel forwarding for efficient bandwidth utilization in networks-on-chip
KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems. Mälardalen University (MDH), Sweden.ORCID iD: 0000-0001-6289-1521
2017 (English)In: 30th International Conference on Architecture of Computing Systems, ARCS 2017, Springer Verlag , 2017, p. 152-163Conference paper, Published paper (Refereed)
Abstract [en]

Networks-on-chip (NoC) provide a scalable and power-efficient communication infrastructure for different computing chips, ranging from fully customized multi/many-processor systems-on-chip (MPSoCs) to general-purpose chip multiprocessors (CMPs). A common aspect in almost all NoC workloads is the varying size of data transmitted by each transaction: while large data blocks are transferred as multiple-flit packets, a part of the traffic consists of short data segment (control data) that does not even fill a single flit. In conventional NoCs, switch allocator assigns/ grants a switch output (and the link connected to it) to a single flit at each cycle, even if the flit is shorter than the link bit-width. In this paper, we propose a novel NoC architecture that enables routers to simultaneously send two short flits on the same link, effectively utilizing the link bandwidth that otherwise would be wasted. To this end, new crossbar, virtual channel (VC), and switch allocator architectures are presented to support parallel short packet forwarding on NoC links. Simulation results using synthetic and realistic workloads show that the proposed architecture improves the NoC performance by up to 24%.

Place, publisher, year, edition, pages
Springer Verlag , 2017. p. 152-163
Keywords [en]
Bandwidth utilization, Heterogeneous packet size, Network-on-Chip, Bandwidth, Communication channels (information theory), Computer architecture, Network architecture, Routers, Servers, System-on-chip, Band-width utilization, Efficient bandwidth, General purpose chips, NoC architectures, Packet size, Parallel forwarding, Power-efficient communications, Proposed architectures
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-207432DOI: 10.1007/978-3-319-54999-6_12Scopus ID: 2-s2.0-85014843599ISBN: 9783319549989 (print)OAI: oai:DiVA.org:kth-207432DiVA, id: diva2:1098248
Conference
3 April 2017 through 6 April 2017
Note

QC 20170523

Available from: 2017-05-23 Created: 2017-05-23 Last updated: 2017-05-23Bibliographically approved

Open Access in DiVA

No full text in DiVA

Other links

Publisher's full textScopus

Authority records BETA

Daneshtalab, Masoud

Search in DiVA

By author/editor
Daneshtalab, Masoud
By organisation
Electronic and embedded systems
Computer Systems

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 138 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf