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Round-trip DRAM access fairness in 3D NoC-based many-core systems
KTH, Skolan för elektro- och systemteknik (EES).
KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.ORCID-id: 0000-0003-0061-3475
2017 (Engelska)Ingår i: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 16, nr 5s, artikel-id 162Artikel i tidskrift (Refereegranskat) Published
Abstract [en]

In 3D NoC-based many-core systems, DRAM accesses behave differently due to their different communication distances and the latency gap of different DRAM accesses becomes bigger as the network size increases, which leads to unfair DRAM access performance among different nodes. This phenomenon may lead to high latencies for some DRAM accesses that become the performance bottleneck of the system. The paper addresses the DRAM access fairness problem in 3D NoC-based many-core systems by narrowing the latency difference of DRAM accesses as well as reducing the maximum latency. Firstly, the latency of a round-trip DRAM access is modeled and the factors causing DRAM access latency difference are discussed in detail. Secondly, the DRAM access fairness is further quantitatively analyzed through experiments. Thirdly, we propose to predict the network latency of round-trip DRAM accesses and use the predicted round-trip DRAM access time as the basis to prioritize the DRAM accesses in DRAM interfaces so that the DRAM accesses with potential high latencies can be transferred as early and fast as possible, thus achieving fair DRAM access. Experiments with synthetic and application workloads validate that our approach can achieve fair DRAM access and outperform the traditional First-Come-First-Serve (FCFS) scheduling policy and the scheduling policies proposed by reference [7] and [24] in terms of maximum latency, Latency Standard Deviation (LSD)1 and speedup. In the experiments, the maximum improvement of the maximum latency, LSD, and speedup are 12.8%, 6.57%, and 8.3% respectively. Besides, our proposal brings very small extra hardware overhead (<0.6%) in comparison to the three counterparts.

Ort, förlag, år, upplaga, sidor
Association for Computing Machinery , 2017. Vol. 16, nr 5s, artikel-id 162
Nyckelord [en]
3D networks-on-chip (NoC), DRAM access fairness, DRAM scheduling, Round-trip, Scheduling, 3D networks, Communication distance, First come first serves, Hardware overheads, Performance bottlenecks, Round trip, Scheduling policies, Standard deviation, Network-on-chip
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URN: urn:nbn:se:kth:diva-216205DOI: 10.1145/3126561ISI: 000414353800045Scopus ID: 2-s2.0-85030680902OAI: oai:DiVA.org:kth-216205DiVA, id: diva2:1167115
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QC 20171218

Tillgänglig från: 2017-12-18 Skapad: 2017-12-18 Senast uppdaterad: 2018-01-13Bibliografiskt granskad

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Chen, XiaowenLu, Zhonghai

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Skolan för elektro- och systemteknik (EES)VinnExcellence Center for Intelligence in Paper and Packaging, iPACKElektronik
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