Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.ORCID iD: 0000-0003-3802-7834
2018 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 05Article in journal (Refereed) Accepted
Abstract [en]

This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

Place, publisher, year, edition, pages
2018. Vol. 05
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
URN: urn:nbn:se:kth:diva-229446DOI: 10.1109/TCSI.2018.2838135ISI: 000448934700002Scopus ID: 2-s2.0-85048023102OAI: oai:DiVA.org:kth-229446DiVA, id: diva2:1213039
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-06-04 Created: 2018-06-04 Last updated: 2019-04-12Bibliographically approved
In thesis
1. Circuit Design Techniques for Implantable Closed-Loop Neural Interfaces
Open this publication in new window or tab >>Circuit Design Techniques for Implantable Closed-Loop Neural Interfaces
2019 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Implantable neural interfaces are microelectronic systems, which have the potential to enable a wide range of applications, such as diagnosis and treatment of neurological disorders. These applications depend on neural interfaces to accurately record electrical activity from the surface of the brain, referred to as electrocorticography (ECoG), and provide controlled electrical stimulation as feedback. Since the electrical activity in the brain is caused by ionic currents in neurons, the bridge between living tissue and inorganic electronics is achieved via microelectrode arrays. The conversion of the ionic charge into freely moving electrons creates a built-in electrode potential that is several orders of magnitude larger than the ECoG signal, which increases the dynamic range, resolution, and power consumption requirements of neural interfaces. Also, the small surface area of microelectrodes implies a high-impedance contact, which can attenuate the ECoG signal. Moreover, the applied electrical stimulation can also interfere with the recording and ultimately cause irreversible damages to the electrodes or change their impedance. This thesis is devoted to resolving the challenges of high-resolution recording and monitoring the electrode impedance in implantable neural interfaces.

The first part of this thesis investigates the state-of-the-art neural interfaces for ECoG and identifies their limitations. As a result of the investigation, a high-resolution ADC is proposed and implemented based on a ΔΣ modulator. In order to enhance performance, dynamic biasing and area-efficient switched-capacitor circuits were proposed. The ΔΣ modulator is combined with the analog front-end to provide a complete readout solution for high-resolution ECoG recording. The corresponding chip prototype was fabricated in a 180 nm CMOS process, and the measurement results showed a 14-ENOB over a 300-Hz bandwidth while dissipating 54-μW.

The second part of this thesis expands upon the well-known methods for impedance measurements and proposes an alternative digital method for monitoring the electrode-tissue interface impedance. The proposed method is based on the system identification technique from adaptive digital filtering, and it is compatible with existing circuitry for neural stimulation. The method is simple to implement and performs wide-band measurements. The system identification was first verified through behavioral simulations and then tested with a board-level prototype in order to validate the functionality under real conditions. The measurement results showed successful identification of the electrode-electrolyte and electrode-skin impedance magnitudes.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2019. p. 72
Series
TRITA-EECS-AVL ; 2019:33
Keywords
Neural interface, ECoG, high-resolution, ADC, recording, delta-sigma modulator, system identification, impedance measurements
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-249435 (URN)978-91-7873-151-0 (ISBN)
Public defence
2019-05-17, Ka-Sal B (Sal Peter Weissglas), Kistagången 16,, Stockholm, 13:00 (English)
Opponent
Supervisors
Funder
Swedish Research CouncilSwedish Foundation for Strategic Research
Note

QC 20190412

Available from: 2019-04-12 Created: 2019-04-12 Last updated: 2019-04-12Bibliographically approved

Open Access in DiVA

fulltext(1862 kB)102 downloads
File information
File name FULLTEXT01.pdfFile size 1862 kBChecksum SHA-512
5ad6a50a46aac340d618cf21342fdbc464276ed99f867fe04ad23df0790074fe299ec2a1e873e993f8c8efdf5334ec3f684af87dc7a8e546af4b736a2253844b
Type fulltextMimetype application/pdf

Other links

Publisher's full textScopusPublisher

Authority records BETA

Ivanisevic, NikolaRodriguez, SaulRusu, Ana

Search in DiVA

By author/editor
Ivanisevic, NikolaRodriguez, SaulRusu, Ana
By organisation
Integrated devices and circuits
In the same journal
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
Other Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
Total: 102 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 2983 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf