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Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.ORCID iD: 0000-0003-3802-7834
2018 (English)Conference paper, Published paper (Refereed)
Abstract [en]

A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is −133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

Place, publisher, year, edition, pages
Florence, Italy: IEEE, 2018.
Series
IEEE International Symposium on Circuits and Systems (ISCAS), E-ISSN 2379-447X
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
URN: urn:nbn:se:kth:diva-229449DOI: 10.1109/ISCAS.2018.8351377ISI: 000451218702062Scopus ID: 2-s2.0-85057071679ISBN: 978-1-5386-4881-0 (electronic)ISBN: 978-1-5386-4882-7 (print)OAI: oai:DiVA.org:kth-229449DiVA, id: diva2:1213046
Conference
IEEE International Symposium on Circuits and Systems (ISCAS) 2018
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-06-04 Created: 2018-06-04 Last updated: 2019-05-07Bibliographically approved
In thesis
1. Circuit Design Techniques for Implantable Closed-Loop Neural Interfaces
Open this publication in new window or tab >>Circuit Design Techniques for Implantable Closed-Loop Neural Interfaces
2019 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Implantable neural interfaces are microelectronic systems, which have the potential to enable a wide range of applications, such as diagnosis and treatment of neurological disorders. These applications depend on neural interfaces to accurately record electrical activity from the surface of the brain, referred to as electrocorticography (ECoG), and provide controlled electrical stimulation as feedback. Since the electrical activity in the brain is caused by ionic currents in neurons, the bridge between living tissue and inorganic electronics is achieved via microelectrode arrays. The conversion of the ionic charge into freely moving electrons creates a built-in electrode potential that is several orders of magnitude larger than the ECoG signal, which increases the dynamic range, resolution, and power consumption requirements of neural interfaces. Also, the small surface area of microelectrodes implies a high-impedance contact, which can attenuate the ECoG signal. Moreover, the applied electrical stimulation can also interfere with the recording and ultimately cause irreversible damages to the electrodes or change their impedance. This thesis is devoted to resolving the challenges of high-resolution recording and monitoring the electrode impedance in implantable neural interfaces.

The first part of this thesis investigates the state-of-the-art neural interfaces for ECoG and identifies their limitations. As a result of the investigation, a high-resolution ADC is proposed and implemented based on a ΔΣ modulator. In order to enhance performance, dynamic biasing and area-efficient switched-capacitor circuits were proposed. The ΔΣ modulator is combined with the analog front-end to provide a complete readout solution for high-resolution ECoG recording. The corresponding chip prototype was fabricated in a 180 nm CMOS process, and the measurement results showed a 14-ENOB over a 300-Hz bandwidth while dissipating 54-μW.

The second part of this thesis expands upon the well-known methods for impedance measurements and proposes an alternative digital method for monitoring the electrode-tissue interface impedance. The proposed method is based on the system identification technique from adaptive digital filtering, and it is compatible with existing circuitry for neural stimulation. The method is simple to implement and performs wide-band measurements. The system identification was first verified through behavioral simulations and then tested with a board-level prototype in order to validate the functionality under real conditions. The measurement results showed successful identification of the electrode-electrolyte and electrode-skin impedance magnitudes.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2019. p. 72
Series
TRITA-EECS-AVL ; 2019:33
Keywords
Neural interface, ECoG, high-resolution, ADC, recording, delta-sigma modulator, system identification, impedance measurements
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-249435 (URN)978-91-7873-151-0 (ISBN)
Public defence
2019-05-17, Ka-Sal B (Sal Peter Weissglas), Kistagången 16,, Stockholm, 13:00 (English)
Opponent
Supervisors
Funder
Swedish Research CouncilSwedish Foundation for Strategic Research
Note

QC 20190412

Available from: 2019-04-12 Created: 2019-04-12 Last updated: 2019-04-12Bibliographically approved

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fulltext(390 kB)294 downloads
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File name FULLTEXT01.pdfFile size 390 kBChecksum SHA-512
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Type fulltextMimetype application/pdf

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Publisher's full textScopushttps://ieeexplore.ieee.org/document/8351377/

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Ivanisevic, NikolaRodriguez, SaulRusu, Ana

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