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A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.ORCID iD: 0000-0002-7534-9317
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.ORCID iD: 0000-0003-0565-9907
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.ORCID iD: 0000-0001-6705-1660
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2018 (English)In: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE conference proceedings, 2018Conference paper, Published paper (Refereed)
Abstract [en]

The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2018.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-235831ISI: 000462960700020Scopus ID: 2-s2.0-85063138253OAI: oai:DiVA.org:kth-235831DiVA, id: diva2:1253818
Conference
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
Note

QC 20181008

Available from: 2018-10-06 Created: 2018-10-06 Last updated: 2019-07-31Bibliographically approved

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fulltext(1024 kB)44 downloads
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Rodriguez, SaulHellström, Per-ErikRusu, Ana

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