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Low-parasitic-capacitance self-aligned 4H-SiC nMOSFETs for harsh environment electronics
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2018 (English)In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 924, p. 971-974Article in journal (Refereed) Published
Abstract [en]

Low-parasitic-capacitance 4H-SiC nMOSFETs using a novel self-aligned process were suggested and demonstrated. In these nMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain, drain-source capacitance) were investigated and low parasitic capacitance was achieved by the self-aligned structure

Place, publisher, year, edition, pages
Trans Tech Publications, 2018. Vol. 924, p. 971-974
Keywords [en]
Harsh environment electronics, Self-aligned Process, SiC nMOSFET, Capacitance, Electric breakdown, MOSFET devices, Silicon carbide, Device characteristics, Drain sources, Harsh environment, Low-parasitic, NMOSFET, Parasitic capacitance, Self aligned process, Self aligned structure, Fluorine compounds
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-236430DOI: 10.4028/www.scientific.net/MSF.924.971Scopus ID: 2-s2.0-85049049901ISBN: 9783035711455 (print)OAI: oai:DiVA.org:kth-236430DiVA, id: diva2:1258777
Note

QC 20181025

Available from: 2018-10-25 Created: 2018-10-25 Last updated: 2018-10-25Bibliographically approved

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Östling, MikaelZetterling, Carl-Mikael

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School of Electrical Engineering and Computer Science (EECS)Integrated devices and circuits
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