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A 3D Tiled Low Power Accelerator for Convolutional Neural Network
KTH, School of Electrical Engineering and Computer Science (EECS). Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
KTH. Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
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2018 (English)In: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2018Conference paper, Published paper (Refereed)
Abstract [en]

It remains a challenge to run Deep Learning in devices with stringent power budget in the Internet-of-Things. This paper presents a low-power accelerator for processing Convolutional Neural Networks on the embedded devices. The power reduction is realized by exploring data reuse in three different aspects, with regards to convolution, filter and input features. A systolic-like data flow is proposed and applied to rows of Processing Elements (PEs), which facilitate reusing the data during convolution. Reuse of input features and filters is achieved by arranging the PE array in a 3D tiled architecture, whose dimension is 3 x 14 x 4. Local storage within PEs is therefore reduced and only cost 17.75 kB, which is 20% of the state-of-the-art. With dedicated delay chains in each PE, this accelerator is reconfigurable to suit various parameter settings of convolutional layers. Evaluated in UMC 65 nm low leakage process, the accelerator can reach a peak performance of 84 GOPS and consume only 136 mW at 250 Mhz.

Place, publisher, year, edition, pages
IEEE , 2018.
Series
IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-240033DOI: 10.1109/ISCAS.2018.8351301ISI: 000451218701203Scopus ID: 2-s2.0-85057087284ISBN: 978-1-5386-4881-0 (print)OAI: oai:DiVA.org:kth-240033DiVA, id: diva2:1269249
Conference
IEEE International Symposium on Circuits and Systems (ISCAS), MAY 27-30, 2018, Florence, ITALY
Note

QC 20181210

Available from: 2018-12-10 Created: 2018-12-10 Last updated: 2019-08-20Bibliographically approved

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Huan, YuxiangZheng, Li-rongTenhunen, Hannu

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School of Electrical Engineering and Computer Science (EECS)KTHIntegrated devices and circuits
Electrical Engineering, Electronic Engineering, Information Engineering

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Citation style
  • apa
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