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TMR Group Coding Method for Optimized SEU and MBU Tolerant Memory Design
Fudan Univ, Shanghai, Peoples R China..
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Fudan Univ, Shanghai, Peoples R China..
Fudan Univ, Shanghai, Peoples R China..
Fudan Univ, Shanghai, Peoples R China..
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2018 (English)In: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2018Conference paper, Published paper (Refereed)
Abstract [en]

This work proposes a fault tolerant memory design using the method of Triple Module Redundancy (TMR) group coding to tolerant the Single-Event Upset (SEU) and Multi-Bit Upset (MBU) influence on memory devices in space environment. The group coding method uses different models to partition and code each word line in memory with Hamming code to achieve best performance. TMR group coding method further increases the capability of self-correction for the errors occurred in parity bits. The evaluation results show that the suggested approach can obtain improved correctness for the memory output with optimized tradeoff between reliability and cost. At 5% error rate, the probability of correct output reaches 70.78% with small cost increment. To achieve 90% reliability, the accuracy improvement is 31.9% compared to TMR with 9% increased area. This solution proposed is evaluated on the memory rich micro-coded processor, but can be further extended to other memory-based processors that need high reliability for the SEU and MBU influence in aerospace applications.

Place, publisher, year, edition, pages
IEEE , 2018.
Series
IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-240035DOI: 10.1109/ISCAS.2018.8351105ISI: 000451218701010Scopus ID: 2-s2.0-85057090538ISBN: 978-1-5386-4881-0 (print)OAI: oai:DiVA.org:kth-240035DiVA, id: diva2:1269250
Conference
IEEE International Symposium on Circuits and Systems (ISCAS), MAY 27-30, 2018, Florence, ITALY
Note

QC 20181210

Available from: 2018-12-10 Created: 2018-12-10 Last updated: 2019-04-09Bibliographically approved

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Zheng, Li-rong

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CiteExportLink to record
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